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authormeissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4>2015-08-24 19:11:02 +0000
committermeissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4>2015-08-24 19:11:02 +0000
commit4f33beb92a364093a41f566c600911f1df934e48 (patch)
treef3302c20285685e439f1bd1aebd47830ee958261 /gcc/config/rs6000/rs6000-cpus.def
parent275ab007db73f26a1c1c44e523c1343e733357b1 (diff)
downloadgcc-4f33beb92a364093a41f566c600911f1df934e48.tar.gz
[gcc]
2015-08-24 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/67211 * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Set -mefficient-unaligned-vsx on ISA 2.7. * config/rs6000/rs6000.opt (-mefficient-unaligned-vsx): Convert option to a masked option. * config/rs6000/rs6000.c (rs6000_option_override_internal): Rework logic for -mefficient-unaligned-vsx so that it is set via an arch ISA option, instead of being set if -mtune=power8 is set. Move -mefficient-unaligned-vsx and -mallow-movmisalign handling to be near other default option handling. [gcc/testsuite] 2015-08-24 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/67211 * g++.dg/pr67211.C: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-5-branch@227146 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000/rs6000-cpus.def')
-rw-r--r--gcc/config/rs6000/rs6000-cpus.def2
1 files changed, 2 insertions, 0 deletions
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 9fd565286f2..03764aef740 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -53,6 +53,7 @@
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DIRECT_MOVE \
+ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_HTM \
| OPTION_MASK_QUAD_MEMORY \
| OPTION_MASK_QUAD_MEMORY_ATOMIC \
@@ -78,6 +79,7 @@
| OPTION_MASK_DFP \
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_DLMZB \
+ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FPRND \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \