diff options
| author | kelvin <kelvin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-10-18 19:31:38 +0000 |
|---|---|---|
| committer | kelvin <kelvin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-10-18 19:31:38 +0000 |
| commit | f9debd38da478845163fba8d354a983eb9f4b33f (patch) | |
| tree | 98cfcb2955599293e2973f60bf60e0c60c79ea9e /gcc/config/rs6000/rs6000-builtin.def | |
| parent | 5dc8060ec69494d437bf6e53deeab9d62d363af7 (diff) | |
| download | gcc-f9debd38da478845163fba8d354a983eb9f4b33f.tar.gz | |
gcc/testsuite/ChangeLog:
2016-10-18 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/vsu/vec-all-ne-0.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-1.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-10.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-11.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-12.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-13.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-14.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-2.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-3.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-4.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-5.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-6.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-7.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-8.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-9.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-1.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-2.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-3.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-4.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-5.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-6.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-7.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-0.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-1.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-10.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-11.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-12.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-13.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-14.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-2.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-3.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-4.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-5.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-6.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-7.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-8.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-9.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-1.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-2.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-3.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-4.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-5.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-6.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-7.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-0.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-1.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-2.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-3.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-4.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-5.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-6.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-8.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-9.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-1.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-2.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-3.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-4.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-5.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-6.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-7.c: New test.
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c: New test.
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c: New test.
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c: New test.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c: New test.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c: New test.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-0.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-1.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-10.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-11.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-12.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-13.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-2.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-3.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-4.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-5.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-6.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-7.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-8.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-9.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-0.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-1.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-2.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-3.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-4.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-5.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-6.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-7.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-0.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-1.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-2.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-3.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-4.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-5.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-6.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-7.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-0.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-1.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-10.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-11.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-12.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-13.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-2.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-3.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-4.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-5.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-6.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-7.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-8.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-9.c: New test.
* gcc.target/powerpc/vsu/vsu.exp: New file.
gcc/ChangeLog:
2016-10-18 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/altivec.h (vec_xl_len): New macro.
(vec_xst_len): New macro.
(vec_cmpnez): New macro.
(vec_cntlz_lsbb): New macro.
(vec_cnttz_lsbb): New macro.
(vec_xlx): New macro.
(vec_xrx): New macro.
(vec_all_nez): New C++ predicate template.
(vec_any_eqz): New C++ predicate template.
(vec_all_ne): Revised C++ predicate template under _ARCH_PWR9
conditional compilation.
(vec_any_eq): Revised C++ predicate template under _ARCH_PWR9
conditional compilation.
(vec_all_nez): New macro.
(vec_any_eqz): New macro.
(vec_all_ne): Revised macro under _ARCH_PWR9 conditional
compilation.
(vec_any_eq): Revised macro under _ARCH_PWR9 conditional
compilation.
* config/rs6000/vector.md (VI): Moved this mode iterator
definition from altivec.md to vector.md.
(UNSPEC_NEZ_P): New value.
(vector_ne_<mode>_p): New expansion for implementation of
vec_all_ne and vec_any_eq built-in functions.
(vector_nez_<mode>_p): New expansion for implementation of
vec_all_nez and vec_any_eqz built-in functions.
(vector_ne_v2di_p): New expansion for implementation of vec_all_ne
and vec_any_eq built-in function.
(cr6_test_for_zero): New commentary to explain this expansion.
(cr6_test_for_zero_reverse): New commentary to explain this expansion.
(cr6_test_for_lt): New commentary to explain this expansion.
(cr6_test_for_lt_reverse): New commentary to explain this
expansion.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
overloaded function prototypes for vec_all_ne, vec_all_nez,
vec_any_eq, vec_any_eqz, vec_cmpnez, vec_cntlz_lsbb,
vec_cnttz_lsbb, vec_xl_len, vec_xst_len, vec_xlx, and vec_xrx
built-in functions.
(altivec_resolve_overloaded_builtin): Modify the handling of
ALTIVEC_BUILTIN_VEC_CMPNE to use the Power9 instructions when
the compiler is configured to support TARGET_P9_VECTOR.
* config/rs6000/rs6000-builtin.def (BU_ALTIVEC_P): Add commentary
to explain the special processing that is given to predicate
built-ins introduced using this macro.
(BU_ALTIVEC_OVERLOAD_P): Add commentary to alert maintainers to
the special processing given to predicate built-ins introduced
using this macro.
(BU_VSX_P): Likewise.
(BU_P8V_AV_P): Likewise.
(BU_P9V_AV_P): Likewise.
(BU_P9V_AV_X): New macro.
(BU_P9V_64BIT_AV_X): New macro.
(BU_P9V_VSX_3): New macro.
(BU_P9V_OVERLOAD_P): New macro.
(LXVL): New BU_P9V_64BIT_VSX_2.
(VEXTUBLX): New BU_P9V_AV_2.
(VEXTUBRX): Likewise.
(VEXTUHLX): Likewise.
(VEXTUHRX): Likewise.
(VEXTUWLX): Likewise.
(VEXTUWRX): Likewise.
(STXVL): New BU_P9V_64BIT_AV_X.
(VCLZLSBB): New BU_P9V_AV_1.
(VCTZLSBB): Likewise.
(CMPNEB): New BU_P9V_AV_2.
(CMPNEH): Likewise.
(CMPNEW): Likewise.
(CMPNEF): Likewise.
(CMPNED): Likewise.
(VCMPNEB_P): New BU_P9V_AV_P.
(VCMPNEH_P): Likewise.
(VCMPNEW_P): Likewise.
(VCMPNED_P): Likewise.
(VCMPNEFP_P): Likewise.
(VCMPNEDP_P): Likewise.
(CMPNEZB): New BU_P9V_AV_2.
(CMPNEZH): Likewise.
(CMPNEZW): Likewise.
(VCMPNEZB_P): New BU_P9V_AV_P.
(VCMPNEZH_P): Likewise.
(VCMPNEZW_P): Likewise.
(LXVL): New BU_P9V_OVERLOAD_2.
(STXVL): New BU_P9V_OVERLOAD_3.
(VEXTULX): New BU_P9V_OVERLOAD_2.
(VEXTURX): Likewise.
(CMPNEZ): Likewise.
(VCMPNEZ_P): New BU_P9V_OVERLOAD_P.
(VCMPNE_P): Likewise.
(VCLZLSBB): New BU_P9V_OVERLOAD_1.
(VCTZLSBB): Likewise.
* config/rs6000/rs6000.c (altivec_expand_predicate_builtin): Add
comment to explain mode used for scratch register.
(altivec_expand_stxvl_builtin): New function.
(altivec_expand_builtin): Add case for new constant P9V_BUILTIN_STXVL.
(altivec_init_builtins): Add initialized variable
void_ftype_v16qi_pvoid_long and use this type to define the
built-in function __builtin_altivec_stxvl.
* config/rs6000/vsx.md (UNSPEC_LXVL): New value.
(UNSPEC_STXVL): New value.
(UNSPEC_VCLZLSBB): New value.
(UNSPEC_VCTZLSBB): New value.
(UNSPEC_VEXTUBLX): New value.
(UNSPEC_VEXTUHLX): New value.
(UNSPEC_VEXTUWLX): New value.
(UNSPEC_VEXTUBRX): New value.
(UNSPEC_VEXTUHRX): New value.
(UNSPEC_VEXTUWRX): New value.
(UNSPEC_VCMPNEB): New value.
(UNSPEC_VCMPNEZB): New value.
(UNSPEC_VCMPNEH): New value.
(UNSPEC_VCMPNEZH): New value.
(UNSPEC_VCMPNEW): New value.
(UNSPEC_VCMPNEZW): New value.
(*vsx_ne_<mode>_p): New insn for vector test all not equal with
vector of integer modes.
(*vsx_ne_<mode>_p): New insn for vector test all not equal with
vector of float or double modes.
(*vector_nez_<mode>_p): New insn for vector test all not equal or
zero.
(lxvl): New expand for load VSX vector with length.
(*lxvl): New insn for load VSX vector with length.
(stxvl): New expand for store VSX vector with length.
(*stxvl): New insn for store VSX vector with length.
(vcmpneb): New insn for vector of byte compare not equal.
(vcmpnezb): New insn for vector of byte compare not equal or zero.
(vcmpneh): New insn for vector of half word compare not equal.
(vcmpnezh): New insn for vector of half word compare not equal or
zero.
(vcmpnew): New insn for vector of word compare not equal.
(vcmpne<VSs>): New insn for vector of float or double compare not
equal.
(vcmpnezw): New insn for vector of word compare not equal or zero.
(vclzlsbb): New insn for vector count leading zero
least-significant bits byte.
(vctzlsbb): New insn for vector count trailing zero least
signficant bits byte.
(vextublx): New insn for vector extract unsigned byte left
indexed.
(vextubrx): New insn for vector extract unsigned byte right
indexed.
(vextuhlx): New insn for vector extract unsigned half word left
indexed.
(vextuhrx): New insn for vector extract unsigned half word right
indexed.
(vextuwlx): New insn for vector extract unsigned word left
indexed.
(vextuwrx): New insn for vector extract unsigned word right
indexed.
* config/rs6000/rs6000.h (RS6000_BTC_CONST): Enhance comment to
clarify intent of this constant.
* config/rs6000/altivec.md (VI): Move this mode iterator to vsx.md.
* doc/extend.texi (PowerPC Altivec Built-in Functions): Add
documentation for vec_all_nez, vec_any_eqz, vec_cmpnez,
vec_cntlz_lsbb, vec_cnttz_lsbb, vec_xl_len, vec_xst_len, vec_xlx,
and vec_xrx functions.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241314 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000/rs6000-builtin.def')
| -rw-r--r-- | gcc/config/rs6000/rs6000-builtin.def | 132 |
1 files changed, 132 insertions, 0 deletions
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index e1d53f11708..d21f27580a7 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -137,6 +137,32 @@ | RS6000_BTC_DST), \ CODE_FOR_ ## ICODE) /* ICODE */ +/* All builtins defined with the RS6000_BUILTIN_P macro expect three + arguments, the first of which is an integer constant that clarifies + the implementation's use of CR6 flags. The integer constant + argument may have four values: __CR6_EQ (0) means the predicate is + considered true if the equality-test flag of the CR6 condition + register is true following execution of the code identified by the + ICODE pattern, __CR_EQ_REV (1) means the predicate is considered + true if the equality-test flag is false, __CR6_LT (2) means the + predicate is considered true if the less-than-test flag is true, and + __CR6_LT_REV (3) means the predicate is considered true if the + less-than-test flag is false. For all builtins defined by this + macro, the pattern selected by ICODE expects three operands, a + target and two inputs and is presumed to overwrite the flags of + condition register CR6 as a side effect of computing a result into + the target register. However, the built-in invocation provides + four operands, a target, an integer constant mode, and two inputs. + The second and third operands of the built-in function's invocation + are automatically mapped into operands 1 and 2 of the pattern + identifed by the ICODE argument and additional code is emitted, + depending on the value of the constant integer first argument. + This special processing happens within the implementation of + altivec_expand_predicate_builtin(), which is defined within + rs6000.c. The implementation of altivec_expand_predicate_builtin() + allocates a scratch register having the same mode as operand 0 to hold + the result produced by evaluating ICODE. */ + #define BU_ALTIVEC_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_P (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ @@ -203,6 +229,7 @@ | RS6000_BTC_DST), \ CODE_FOR_nothing) /* ICODE */ +/* See the comment on BU_ALTIVEC_P. */ #define BU_ALTIVEC_OVERLOAD_P(ENUM, NAME) \ RS6000_BUILTIN_P (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ @@ -252,6 +279,7 @@ | RS6000_BTC_ABS), \ CODE_FOR_ ## ICODE) /* ICODE */ +/* See the comment on BU_ALTIVEC_P. */ #define BU_VSX_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_P (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ @@ -338,6 +366,7 @@ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ +/* See the comment on BU_ALTIVEC_P. */ #define BU_P8V_AV_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_P (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ @@ -781,6 +810,7 @@ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ +/* See the comment on BU_ALTIVEC_P. */ #define BU_P9V_AV_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_P (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ @@ -789,6 +819,23 @@ | RS6000_BTC_PREDICATE), \ CODE_FOR_ ## ICODE) /* ICODE */ +#define BU_P9V_AV_X(ENUM, NAME, ATTR) \ + RS6000_BUILTIN_X (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_altivec_" NAME, /* NAME */ \ + RS6000_BTM_P9_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_SPECIAL), \ + CODE_FOR_nothing) /* ICODE */ + +#define BU_P9V_64BIT_AV_X(ENUM, NAME, ATTR) \ + RS6000_BUILTIN_X (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_altivec_" NAME, /* NAME */ \ + (RS6000_BTM_P9_VECTOR \ + | RS6000_BTM_64BIT), /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_SPECIAL), \ + CODE_FOR_nothing) /* ICODE */ + /* For the instructions encoded as VSX instructions use __builtin_vsx as the builtin name. */ #define BU_P9V_VSX_1(ENUM, NAME, ATTR, ICODE) \ @@ -825,6 +872,23 @@ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ +#define BU_P9V_VSX_3(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_3 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_vsx_" NAME, /* NAME */ \ + RS6000_BTM_P9_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +/* See the comment on BU_ALTIVEC_P. */ +#define BU_P9V_OVERLOAD_P(ENUM, NAME) \ + RS6000_BUILTIN_P (P9V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ + "__builtin_vec_" NAME, /* NAME */ \ + RS6000_BTM_ALTIVEC, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_PREDICATE), \ + CODE_FOR_nothing) /* ICODE */ + #define BU_P9V_OVERLOAD_1(ENUM, NAME) \ RS6000_BUILTIN_1 (P9V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ @@ -1893,6 +1957,74 @@ BU_P9V_OVERLOAD_2 (VIE, "insert_exp") BU_P9V_OVERLOAD_2 (VIEDP, "insert_exp_dp") BU_P9V_OVERLOAD_2 (VIESP, "insert_exp_sp") +/* 2 argument vector functions added in ISA 3.0 (power9). */ +BU_P9V_64BIT_VSX_2 (LXVL, "lxvl", CONST, lxvl) + +BU_P9V_AV_2 (VEXTUBLX, "vextublx", CONST, vextublx) +BU_P9V_AV_2 (VEXTUBRX, "vextubrx", CONST, vextubrx) +BU_P9V_AV_2 (VEXTUHLX, "vextuhlx", CONST, vextuhlx) +BU_P9V_AV_2 (VEXTUHRX, "vextuhrx", CONST, vextuhrx) +BU_P9V_AV_2 (VEXTUWLX, "vextuwlx", CONST, vextuwlx) +BU_P9V_AV_2 (VEXTUWRX, "vextuwrx", CONST, vextuwrx) + +/* 3 argument vector functions returning void, treated as SPECIAL, + added in ISA 3.0 (power9). */ +BU_P9V_64BIT_AV_X (STXVL, "stxvl", MISC) + +/* 1 argument vector functions added in ISA 3.0 (power9). */ +BU_P9V_AV_1 (VCLZLSBB, "vclzlsbb", CONST, vclzlsbb) +BU_P9V_AV_1 (VCTZLSBB, "vctzlsbb", CONST, vctzlsbb) + +/* Built-in support for Power9 "VSU option" string operations includes + new awareness of the "vector compare not equal" (vcmpneb, vcmpneb., + vcmpneh, vcmpneh., vcmpnew, vcmpnew.) and "vector compare + not equal or zero" (vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh., + vcmpnezw, vcmpnezw.) instructions. For consistency with existing + infrastructure, this new awareness is integrated in the style of + earlier implementations of the __builtin_vec_cmpne and + __builtin_vec_cmpeq_p functions. */ + +BU_P9V_AV_2 (CMPNEB, "vcmpneb", CONST, vcmpneb) +BU_P9V_AV_2 (CMPNEH, "vcmpneh", CONST, vcmpneh) +BU_P9V_AV_2 (CMPNEW, "vcmpnew", CONST, vcmpnew) +BU_P9V_AV_2 (CMPNEF, "vcmpnef", CONST, vcmpnesp) +BU_P9V_AV_2 (CMPNED, "vcmpned", CONST, vcmpnedp) + +BU_P9V_AV_P (VCMPNEB_P, "vcmpneb_p", CONST, vector_ne_v16qi_p) +BU_P9V_AV_P (VCMPNEH_P, "vcmpneh_p", CONST, vector_ne_v8hi_p) +BU_P9V_AV_P (VCMPNEW_P, "vcmpnew_p", CONST, vector_ne_v4si_p) +BU_P9V_AV_P (VCMPNED_P, "vcmpned_p", CONST, vector_ne_v2di_p) + +BU_P9V_AV_P (VCMPNEFP_P, "vcmpnefp_p", CONST, vector_ne_v4sf_p) +BU_P9V_AV_P (VCMPNEDP_P, "vcmpnedp_p", CONST, vector_ne_v2df_p) + +BU_P9V_AV_2 (CMPNEZB, "vcmpnezb", CONST, vcmpnezb) +BU_P9V_AV_2 (CMPNEZH, "vcmpnezh", CONST, vcmpnezh) +BU_P9V_AV_2 (CMPNEZW, "vcmpnezw", CONST, vcmpnezw) + +BU_P9V_AV_P (VCMPNEZB_P, "vcmpnezb_p", CONST, vector_nez_v16qi_p) +BU_P9V_AV_P (VCMPNEZH_P, "vcmpnezh_p", CONST, vector_nez_v8hi_p) +BU_P9V_AV_P (VCMPNEZW_P, "vcmpnezw_p", CONST, vector_nez_v4si_p) + +/* ISA 3.0 Vector scalar overloaded 2 argument functions */ +BU_P9V_OVERLOAD_2 (LXVL, "lxvl") + +/* ISA 3.0 Vector scalar overloaded 3 argument functions */ +BU_P9V_OVERLOAD_3 (STXVL, "stxvl") + +BU_P9V_OVERLOAD_2 (VEXTULX, "vextulx") +BU_P9V_OVERLOAD_2 (VEXTURX, "vexturx") + +/* Overloaded CMPNE support was implemented prior to Power 9, + so is not mentioned here. */ +BU_P9V_OVERLOAD_2 (CMPNEZ, "vcmpnez") + +BU_P9V_OVERLOAD_P (VCMPNEZ_P, "vcmpnez_p") +BU_P9V_OVERLOAD_P (VCMPNE_P, "vcmpne_p") + +/* ISA 3.0 Vector scalar overloaded 1 argument functions */ +BU_P9V_OVERLOAD_1 (VCLZLSBB, "vclzlsbb") +BU_P9V_OVERLOAD_1 (VCTZLSBB, "vctzlsbb") /* 2 argument extended divide functions added in ISA 2.06. */ BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si) |