2009-04-13 Vladimir Makarov <vmakarov@redhat.com>

	* genautomata.c: Put blank after comma.
	(automaton_decls): New.
	(struct unit_usage): Add comments to member next.
	(store_alt_unit_usage): Keep the list ordered.
	(unit_present_on_list_p, equal_alternatives_p): New.
	(check_regexp_units_distribution): Check units distribution
	correctness correctly.
	(main): Don't write automata if error is found.  Return correct
	exit code.
	
	* config/m68k/cf.md (cfv4_ds): Remove.
	(cfv4_pOEP1, cfv4_sOEP1, cfv4_pOEP2,cfv4_sOEP2, cfv4_pOEP3,
	cfv4_sOEP3): Assign to cfv4_oep instead of cfv4_ds.

	* config/rs6000/power4.md (lsuq_power4, iq_power4, fpq_power4,
	power4-load-ext, power4-store, power4-store-update,
	power4-fpstore, power4-fpstore-update, power4-two, power4-three,
	power4-insert, power4-compare, power4-lmul-cmp, power4-imul-cmp,
	power4-lmul, , power4-imul, power4-imul3, power4-sdiv,
	power4-sqrt, power4-isync): Modify reservation to make correct
	unit distribution to automata.

	* config/rs6000/power5.md (iq_power5, fpq_power5, power5-store,
	power5-store-update, power5-two, power5-three, power5-lmul,
	power5-imul, power5-imul3, power5-sdiv, power5-sqrt): Ditto.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@146010 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 35 insertions, 48 deletions

diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md
index 1b73e093e6e..83ffabcfb3a 100644
--- a/gcc/config/rs6000/power5.md
+++ b/gcc/config/rs6000/power5.md
@@ -40,16 +40,12 @@
 		    |(du4_power5,lsu1_power5)")
 
 (define_reservation "iq_power5"
-		    "(du1_power5,iu1_power5)\
-		    |(du2_power5,iu2_power5)\
-		    |(du3_power5,iu2_power5)\
-		    |(du4_power5,iu1_power5)")
+		    "(du1_power5|du2_power5|du3_power5|du4_power5),\
+                     (iu1_power5|iu2_power5)")
 
 (define_reservation "fpq_power5"
-		    "(du1_power5,fpu1_power5)\
-		    |(du2_power5,fpu2_power5)\
-		    |(du3_power5,fpu2_power5)\
-		    |(du4_power5,fpu1_power5)")
+		    "(du1_power5|du2_power5|du3_power5|du4_power5),\
+                     (fpu1_power5|fpu2_power5)")
 
 ; Dispatch slots are allocated in order conforming to program order.
 (absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5")
@@ -105,10 +101,11 @@
 (define_insn_reservation "power5-store" 12
   (and (eq_attr "type" "store")
        (eq_attr "cpu" "power5"))
-  "(du1_power5,lsu1_power5,iu1_power5)\
-  |(du2_power5,lsu2_power5,iu2_power5)\
-  |(du3_power5,lsu2_power5,iu2_power5)\
-  |(du4_power5,lsu1_power5,iu1_power5)")
+  "((du1_power5,lsu1_power5)\
+    |(du2_power5,lsu2_power5)\
+    |(du3_power5,lsu2_power5)\
+    |(du4_power5,lsu1_power5)),\
+    (iu1_power5|iu2_power5)")
 
 (define_insn_reservation "power5-store-update" 12
   (and (eq_attr "type" "store_u")
@@ -124,10 +121,11 @@
 (define_insn_reservation "power5-fpstore" 12
   (and (eq_attr "type" "fpstore")
        (eq_attr "cpu" "power5"))
-  "(du1_power5,lsu1_power5,fpu1_power5)\
-  |(du2_power5,lsu2_power5,fpu2_power5)\
-  |(du3_power5,lsu2_power5,fpu2_power5)\
-  |(du4_power5,lsu1_power5,fpu1_power5)")
+  "((du1_power5,lsu1_power5)\
+    |(du2_power5,lsu2_power5)\
+    |(du3_power5,lsu2_power5)\
+    |(du4_power5,lsu1_power5)),\
+    (fpu1_power5|fpu2_power5)")
 
 (define_insn_reservation "power5-fpstore-update" 12
   (and (eq_attr "type" "fpstore_u,fpstore_ux")
@@ -151,22 +149,24 @@
 (define_insn_reservation "power5-two" 2
   (and (eq_attr "type" "two")
        (eq_attr "cpu" "power5"))
-  "(du1_power5+du2_power5,iu1_power5,nothing,iu2_power5)\
-  |(du2_power5+du3_power5,iu2_power5,nothing,iu2_power5)\
-  |(du3_power5+du4_power5,iu2_power5,nothing,iu1_power5)\
-  |(du4_power5+du1_power5,iu1_power5,nothing,iu1_power5)")
+  "((du1_power5+du2_power5)\
+    |(du2_power5+du3_power5)\
+    |(du3_power5+du4_power5)\
+    |(du4_power5+du1_power5)),\
+    ((iu1_power5,nothing,iu2_power5)\
+     |(iu2_power5,nothing,iu2_power5)\
+     |(iu2_power5,nothing,iu1_power5)\
+     |(iu1_power5,nothing,iu1_power5))")
 
 (define_insn_reservation "power5-three" 2
   (and (eq_attr "type" "three")
        (eq_attr "cpu" "power5"))
-  "(du1_power5+du2_power5+du3_power5,\
-    iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
-  |(du2_power5+du3_power5+du4_power5,\
-    iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
-  |(du3_power5+du4_power5+du1_power5,\
-    iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
-  |(du4_power5+du1_power5+du2_power5,\
-    iu1_power5,nothing,iu2_power5,nothing,iu2_power5)")
+  "(du1_power5+du2_power5+du3_power5|du2_power5+du3_power5+du4_power5\
+    |du3_power5+du4_power5+du1_power5|du4_power5+du1_power5+du2_power5),\
+   ((iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
+    |(iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
+    |(iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
+    |(iu1_power5,nothing,iu2_power5,nothing,iu2_power5))")
 
 (define_insn_reservation "power5-insert" 4
   (and (eq_attr "type" "insert_word")
@@ -202,26 +202,17 @@
 (define_insn_reservation "power5-lmul" 7
   (and (eq_attr "type" "lmul")
        (eq_attr "cpu" "power5"))
-  "(du1_power5,iu1_power5*6)\
-  |(du2_power5,iu2_power5*6)\
-  |(du3_power5,iu2_power5*6)\
-  |(du4_power5,iu1_power5*6)")
+  "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*6|iu2_power5*6)")
 
 (define_insn_reservation "power5-imul" 5
   (and (eq_attr "type" "imul")
        (eq_attr "cpu" "power5"))
-  "(du1_power5,iu1_power5*4)\
-  |(du2_power5,iu2_power5*4)\
-  |(du3_power5,iu2_power5*4)\
-  |(du4_power5,iu1_power5*4)")
+  "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*4|iu2_power5*4)")
 
 (define_insn_reservation "power5-imul3" 4
   (and (eq_attr "type" "imul2,imul3")
        (eq_attr "cpu" "power5"))
-  "(du1_power5,iu1_power5*3)\
-  |(du2_power5,iu2_power5*3)\
-  |(du3_power5,iu2_power5*3)\
-  |(du4_power5,iu1_power5*3)")
+  "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*3|iu2_power5*3)")
 
 
 ; SPR move only executes in first IU.
@@ -300,18 +291,14 @@
 (define_insn_reservation "power5-sdiv" 33
   (and (eq_attr "type" "sdiv,ddiv")
        (eq_attr "cpu" "power5"))
-  "(du1_power5,fpu1_power5*28)\
-  |(du2_power5,fpu2_power5*28)\
-  |(du3_power5,fpu2_power5*28)\
-  |(du4_power5,fpu1_power5*28)")
+  "(du1_power5|du2_power5|du3_power5|du4_power5),\
+   (fpu1_power5*28|fpu2_power5*28)")
 
 (define_insn_reservation "power5-sqrt" 40
   (and (eq_attr "type" "ssqrt,dsqrt")
        (eq_attr "cpu" "power5"))
-  "(du1_power5,fpu1_power5*35)\
-  |(du2_power5,fpu2_power5*35)\
-  |(du3_power5,fpu2_power5*35)\
-  |(du4_power5,fpu2_power5*35)")
+  "(du1_power5|du2_power5|du3_power5|du4_power5),\
+   (fpu1_power5*35|fpu2_power5*35)")
 
 (define_insn_reservation "power5-isync" 2 
   (and (eq_attr "type" "isync")