diff options
| author | wschmidt <wschmidt@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-02-03 01:26:34 +0000 |
|---|---|---|
| committer | wschmidt <wschmidt@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-02-03 01:26:34 +0000 |
| commit | 47f833a22e74dfca99b24631ecc707df126a215a (patch) | |
| tree | 088378e522bddf3e0e950b3507891f3e858f48df /gcc/config/rs6000/altivec.md | |
| parent | 6c65ab3540cd56a0dcc7cbed4b7e4202e9dd3afa (diff) | |
| download | gcc-47f833a22e74dfca99b24631ecc707df126a215a.tar.gz | |
gcc:
2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (altivec_expand_vec_perm_le): Generalize
for vector types other than V16QImode.
* config/rs6000/altivec.md (altivec_vperm_<mode>): Change to a
define_expand, and call altivec_expand_vec_perm_le when producing
code with little endian element order.
(*altivec_vperm_<mode>_internal): New insn having previous
behavior of altivec_vperm_<mode>.
(altivec_vperm_<mode>_uns): Change to a define_expand, and call
altivec_expand_vec_perm_le when producing code with little endian
element order.
(*altivec_vperm_<mode>_uns_internal): New insn having previous
behavior of altivec_vperm_<mode>_uns.
gcc/testsuite:
2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* gcc.dg/vmx/3b-15.c: Remove special handling for little endian.
* gcc.dg/vmx/perm.c: New.
* gcc.dg/vmx/perm-be-order.c: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@207415 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000/altivec.md')
| -rw-r--r-- | gcc/config/rs6000/altivec.md | 34 |
1 files changed, 32 insertions, 2 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index ac69ac2d635..8a8753ff900 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1826,7 +1826,22 @@ "vrfiz %0,%1" [(set_attr "type" "vecfloat")]) -(define_insn "altivec_vperm_<mode>" +(define_expand "altivec_vperm_<mode>" + [(set (match_operand:VM 0 "register_operand" "=v") + (unspec:VM [(match_operand:VM 1 "register_operand" "v") + (match_operand:VM 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] + UNSPEC_VPERM))] + "TARGET_ALTIVEC" +{ + if (!VECTOR_ELT_ORDER_BIG) + { + altivec_expand_vec_perm_le (operands); + DONE; + } +}) + +(define_insn "*altivec_vperm_<mode>_internal" [(set (match_operand:VM 0 "register_operand" "=v") (unspec:VM [(match_operand:VM 1 "register_operand" "v") (match_operand:VM 2 "register_operand" "v") @@ -1836,7 +1851,22 @@ "vperm %0,%1,%2,%3" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vperm_<mode>_uns" +(define_expand "altivec_vperm_<mode>_uns" + [(set (match_operand:VM 0 "register_operand" "=v") + (unspec:VM [(match_operand:VM 1 "register_operand" "v") + (match_operand:VM 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] + UNSPEC_VPERM_UNS))] + "TARGET_ALTIVEC" +{ + if (!VECTOR_ELT_ORDER_BIG) + { + altivec_expand_vec_perm_le (operands); + DONE; + } +}) + +(define_insn "*altivec_vperm_<mode>_uns_internal" [(set (match_operand:VM 0 "register_operand" "=v") (unspec:VM [(match_operand:VM 1 "register_operand" "v") (match_operand:VM 2 "register_operand" "v") |