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authorH.J. Lu <hjl.tools@gmail.com>2012-06-26 11:54:24 -0700
committerH.J. Lu <hjl.tools@gmail.com>2012-06-26 11:54:24 -0700
commit24fe62c79a89d579257790e268b0b9ea87940a89 (patch)
tree026afc7ae12564c6a1af236b4e76286fe9c79ae9 /gcc/config/rs6000/altivec.md
parent7258422b5896985803cc53aa219b5bfad7115475 (diff)
parentad29bc7a3bd276c44379f4808b75f8449e0ee150 (diff)
downloadgcc-hjl/x32/gcc-4_6-branch.tar.gz
Merge remote-tracking branch 'origin/gcc-4_6-branch' into hjl/x32/gcc-4_6-branchhjl/x32/gcc-4_6-branch
Diffstat (limited to 'gcc/config/rs6000/altivec.md')
-rw-r--r--gcc/config/rs6000/altivec.md16
1 files changed, 8 insertions, 8 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 80e82cc9c29..9fbced17365 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2394,8 +2394,8 @@
(define_insn "altivec_stvlx"
[(parallel
- [(set (match_operand:V4SI 0 "memory_operand" "=Z")
- (match_operand:V4SI 1 "register_operand" "v"))
+ [(set (match_operand:V16QI 0 "memory_operand" "=Z")
+ (match_operand:V16QI 1 "register_operand" "v"))
(unspec [(const_int 0)] UNSPEC_STVLX)])]
"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
"stvlx %1,%y0"
@@ -2403,8 +2403,8 @@
(define_insn "altivec_stvlxl"
[(parallel
- [(set (match_operand:V4SI 0 "memory_operand" "=Z")
- (match_operand:V4SI 1 "register_operand" "v"))
+ [(set (match_operand:V16QI 0 "memory_operand" "=Z")
+ (match_operand:V16QI 1 "register_operand" "v"))
(unspec [(const_int 0)] UNSPEC_STVLXL)])]
"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
"stvlxl %1,%y0"
@@ -2412,8 +2412,8 @@
(define_insn "altivec_stvrx"
[(parallel
- [(set (match_operand:V4SI 0 "memory_operand" "=Z")
- (match_operand:V4SI 1 "register_operand" "v"))
+ [(set (match_operand:V16QI 0 "memory_operand" "=Z")
+ (match_operand:V16QI 1 "register_operand" "v"))
(unspec [(const_int 0)] UNSPEC_STVRX)])]
"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
"stvrx %1,%y0"
@@ -2421,8 +2421,8 @@
(define_insn "altivec_stvrxl"
[(parallel
- [(set (match_operand:V4SI 0 "memory_operand" "=Z")
- (match_operand:V4SI 1 "register_operand" "v"))
+ [(set (match_operand:V16QI 0 "memory_operand" "=Z")
+ (match_operand:V16QI 1 "register_operand" "v"))
(unspec [(const_int 0)] UNSPEC_STVRXL)])]
"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
"stvrxl %1,%y0"