2008-10-01 Andrew Pinski <andrew_pinski@playstation.sony.com>

            Yukishige Shibata <shibata@rd.scei.sony.co.jp>
            Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>

        * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add Cell
        Altivec intrinsics.
        * config/rs6000/rs6000.c (altivec_expand_lv_builtin): Delete
        prototype.  Add new parameter, blk.
        Use BLKmode for the MEM if blk is true.
        (altivec_expand_builtin): Handle ALTIVEC_BUILTIN_STVLX,
        ALTIVEC_BUILTIN_STVLXL, ALTIVEC_BUILTIN_STVRX, and
        ALTIVEC_BUILTIN_STVRXL.
        Update usage of altivec_expand_lv_builtin.
        Handle ALTIVEC_BUILTIN_LVLX, ALTIVEC_BUILTIN_LVLXL,
        ALTIVEC_BUILTIN_LVRX, and ALTIVEC_BUILTIN_LVRXL.
        (altivec_init_builtins): If compiling for the Cell, also define the
        cell VMX builtins.
        * config/rs6000/rs6000.h (rs6000_builtins): Define
        ALTIVEC_BUILTIN_LVLX, ALTIVEC_BUILTIN_LVLXL, ALTIVEC_BUILTIN_LVRX,
        ALTIVEC_BUILTIN_LVRXL, ALTIVEC_BUILTIN_STVLX, ALTIVEC_BUILTIN_STVLXL,
        ALTIVEC_BUILTIN_STVRX, ALTIVEC_BUILTIN_STVRXL,
        ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_VEC_LVLXL,
        ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_VEC_LVRXL,
        ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_VEC_STVLXL,
        ALTIVEC_BUILTIN_VEC_STVRX, and ALTIVEC_BUILTIN_VEC_STVRXL.
        * config/rs6000/altivec.md (define_constants): Define UNSPEC_LVLX,
        UNSPEC_LVLXL, UNSPEC_LVRX, UNSPEC_LVRXL, UNSPEC_STVLX, UNSPEC_STVLXL,
        UNSPEC_STVRX, and UNSPEC_STVRXL.
        (altivec_lvlx): New pattern.
        (altivec_lvlxl): New pattern.
        (altivec_lvrx): New pattern.
        (altivec_lvrxl): New pattern.
        (altivec_stvlx): New pattern.
        (altivec_stvlxl): New pattern.
        (altivec_stvrx): New pattern.
        (altivec_stvrxl): New pattern.
        * config/rs6000/altivec.h (vec_lvlx): Define if PPU is defined.
        (vec_lvlxl): Likewise.
        (vec_lvrx): Define if PPU is defined.
        (vec_lvrxl): Likewise.
        (vec_stvlx): Define if PPU is defined.
        (vec_stvlxl): Likewise.
        (vec_stvrx): Define if PPU is defined.
        (vec_stvrxl): Likewise.

2008-10-01  Andrew Pinski  <andrew_pinski@playstation.sony.com>

        * gcc.target/powerpc/altivec_check.h (altivec_cell_check): New function.
        * gcc.target/powerpc/altivec-cell-6.c: New test.
        * gcc.target/powerpc/altivec-cell-7.c: New test.
        * gcc.target/powerpc/altivec-cell-8.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@140820 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 78 insertions, 0 deletions

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 5edd248b722..9c6245ae8ac 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -130,6 +130,14 @@
    (UNSPEC_INTERLO_V8HI 233)
    (UNSPEC_INTERLO_V16QI 234)
    (UNSPEC_INTERLO_V4SF 235)
+   (UNSPEC_LVLX         236)
+   (UNSPEC_LVLXL        237)
+   (UNSPEC_LVRX         238)
+   (UNSPEC_LVRXL        239)
+   (UNSPEC_STVLX        240)
+   (UNSPEC_STVLXL       241)
+   (UNSPEC_STVRX        242)
+   (UNSPEC_STVRXL       243)
    (UNSPEC_VMULWHUB     308)
    (UNSPEC_VMULWLUB     309)
    (UNSPEC_VMULWHSB     310)
@@ -2677,6 +2685,76 @@
   DONE;
 }")
 
+;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX, LVRXL,
+;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell.
+(define_insn "altivec_lvlx"
+  [(set (match_operand:V16QI 0 "register_operand" "=v")
+        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
+		      UNSPEC_LVLX))]
+  "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
+  "lvlx %0,%y1"
+  [(set_attr "type" "vecload")])
+
+(define_insn "altivec_lvlxl"
+  [(set (match_operand:V16QI 0 "register_operand" "=v")
+        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
+		      UNSPEC_LVLXL))]
+  "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
+  "lvlxl %0,%y1"
+  [(set_attr "type" "vecload")])
+
+(define_insn "altivec_lvrx"
+  [(set (match_operand:V16QI 0 "register_operand" "=v")
+        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
+		      UNSPEC_LVRX))]
+  "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
+  "lvrx %0,%y1"
+  [(set_attr "type" "vecload")])
+
+(define_insn "altivec_lvrxl"
+  [(set (match_operand:V16QI 0 "register_operand" "=v")
+        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
+		      UNSPEC_LVRXL))]
+  "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
+  "lvrxl %0,%y1"
+  [(set_attr "type" "vecload")])
+
+(define_insn "altivec_stvlx"
+  [(parallel
+    [(set (match_operand:V4SI 0 "memory_operand" "=Z")
+	  (match_operand:V4SI 1 "register_operand" "v"))
+     (unspec [(const_int 0)] UNSPEC_STVLX)])]
+  "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
+  "stvlx %1,%y0"
+  [(set_attr "type" "vecstore")])
+
+(define_insn "altivec_stvlxl"
+  [(parallel
+    [(set (match_operand:V4SI 0 "memory_operand" "=Z")
+	  (match_operand:V4SI 1 "register_operand" "v"))
+     (unspec [(const_int 0)] UNSPEC_STVLXL)])]
+  "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
+  "stvlxl %1,%y0"
+  [(set_attr "type" "vecstore")])
+
+(define_insn "altivec_stvrx"
+  [(parallel
+    [(set (match_operand:V4SI 0 "memory_operand" "=Z")
+	  (match_operand:V4SI 1 "register_operand" "v"))
+     (unspec [(const_int 0)] UNSPEC_STVRX)])]
+  "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
+  "stvrx %1,%y0"
+  [(set_attr "type" "vecstore")])
+
+(define_insn "altivec_stvrxl"
+  [(parallel
+    [(set (match_operand:V4SI 0 "memory_operand" "=Z")
+	  (match_operand:V4SI 1 "register_operand" "v"))
+     (unspec [(const_int 0)] UNSPEC_STVRXL)])]
+  "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
+  "stvrxl %1,%y0"
+  [(set_attr "type" "vecstore")])
+
 (define_expand "vec_extract_evenv4si"
  [(set (match_operand:V4SI 0 "register_operand" "")
         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")