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author | dje <dje@138bc75d-0d04-0410-961f-82ee72b054a4> | 2003-02-15 21:19:01 +0000 |
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committer | dje <dje@138bc75d-0d04-0410-961f-82ee72b054a4> | 2003-02-15 21:19:01 +0000 |
commit | a0b983228dda070bf8b24ab3701542bf9bdbeba0 (patch) | |
tree | 889b251db7bddd9347287fabcc0d1c73dd3a30fe /gcc/config/rs6000/7450.md | |
parent | 2a5b4716e2bb96fc20e9790a5e82d4ae4005054c (diff) | |
download | gcc-a0b983228dda070bf8b24ab3701542bf9bdbeba0.tar.gz |
* config/rs6000/rs6000.h (processor_type): Add PPC440.
* config/rs6000/rs6000.c (TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE,
TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD,
TARGET_SCHED_VARIABLE_ISSUE): Define.
(rs6000_use_dfa_pipeline_interface): New function.
(rs6000_multipass_dfa_lookahead): New Function.
(rs6000_variable_issue): New function.
(rs6000_adjust_cost): Add CMP and DELAYED_CR types.
(rs6000_issue_rate): Add PPC440.
* config/rs6000/rs6000.md (unspec list): Correct typo.
(attr "type"): Add load_ext, load_ext_u, load_ext_ux, load_u,
store_ux, store_u, fpload_ux, fpload_u, fpstore_ux, fpstore_u,
cmp, delayed_cr, mfcr, mtcr.
(automata_option): Set "ndfa".
(extendMMNN2): Update attributes.
(movcc_internal1): Discourage move to non-cr0. Update
attributes.
(movMM_update): Update attributes.
(cmpMM_internal): Update attributes.
(sCC CR materialization): Update attributes.
(branch patterns): Do not discourage non-cr0.
(cr logical patterns): Prefer destructive register allocation.
Update attributes.
(movesi_from_cr): Update attribute.
(mtcrf_operation): Update attribute.
(mtcrfsi): Update attribute.
* config/rs6000/40x.md: New file.
* config/rs6000/603.md: New file.
* config/rs6000/6xx.md: New file.
* config/rs6000/7450.md: New file.
* config/rs6000/7xx.md: New file.
* config/rs6000/mpc.md: New file.
* config/rs6000/power4.md: New file.
* config/rs6000/rios1.md: New file.
* config/rs6000/rios2.md: New file.
* config/rs6000/rs64.md: New file.
[Some DFA descriptions based on work by Michael Hayes]
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@62943 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000/7450.md')
-rw-r--r-- | gcc/config/rs6000/7450.md | 137 |
1 files changed, 137 insertions, 0 deletions
diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md new file mode 100644 index 00000000000..12bcbd4ccb5 --- /dev/null +++ b/gcc/config/rs6000/7450.md @@ -0,0 +1,137 @@ +(define_automaton "ppc7450,ppc7450fp,ppc7450other,ppc7450vec") +(define_cpu_unit "iu1_7450,iu2_7450,iu3_7450,mciu_7450" "ppc7450") +(define_cpu_unit "fpu_7450" "ppc7450fp") +(define_cpu_unit "lsu_7450,bpu_7450" "ppc7450other") +(define_cpu_unit "du1_7450,du2_7450,du3_7450" "ppc7450") +(define_cpu_unit "vecsmpl_7450,veccmplx_7450,vecflt_7450,vecperm_7450" "ppc7450vec") +(define_cpu_unit "vdu1_7450,vdu2_7450" "ppc7450vec") + + +;; PPC7450 32-bit 3xIU, MCIU, LSU, SRU, FPU, BPU, 4xVEC +;; IU1,IU2,IU3 can perform all integer operations +;; MCIU performs imul and idiv, cr logical, SPR moves +;; LSU 2 stage pipelined +;; FPU 3 stage pipelined +;; It also has 4 vector units, one for each type of vector instruction. +;; However, we can only dispatch 2 instructions per cycle. +;; Max issue 3 insns/clock cycle (includes 1 branch) +;; In-order execution + +;; Branches go straight to the BPU. All other insns are handled +;; by a dispatch unit which can issue a max of 3 insns per cycle. +(define_reservation "ppc7450_du" "du1_7450|du2_7450|du3_7450") +(define_reservation "ppc7450_vec_du" "vdu1_7450|vdu2_7450") + +(define_insn_reservation "ppc7450-load" 3 + (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\ + load_ux,load_u,vecload") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,lsu_7450") + +(define_insn_reservation "ppc7450-store" 3 + (and (eq_attr "type" "store,store_ux,store_u,vecstore") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,lsu_7450") + +(define_insn_reservation "ppc7450-fpload" 4 + (and (eq_attr "type" "fpload,fpload_ux,fpload_u") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,lsu_7450") + +(define_insn_reservation "ppc7450-fpstore" 3 + (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,lsu_7450*3") + +(define_insn_reservation "ppc7450-integer" 1 + (and (eq_attr "type" "integer") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)") + +(define_insn_reservation "ppc7450-imul" 4 + (and (eq_attr "type" "imul") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,mciu_7450*2") + +(define_insn_reservation "ppc7450-imul2" 3 + (and (eq_attr "type" "imul2,imul3") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,mciu_7450") + +(define_insn_reservation "ppc7450-idiv" 23 + (and (eq_attr "type" "idiv") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,mciu_7450*23") + +(define_insn_reservation "ppc7450-compare" 2 + (and (eq_attr "type" "cmp,compare,delayed_compare") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)") + +(define_insn_reservation "ppc7450-fpcompare" 5 + (and (eq_attr "type" "fpcompare") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,fpu_7450") + +(define_insn_reservation "ppc7450-fp" 5 + (and (eq_attr "type" "fp,dmul") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,fpu_7450") + +; Divides are not pipelined +(define_insn_reservation "ppc7450-sdiv" 21 + (and (eq_attr "type" "sdiv") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,fpu_7450*21") + +(define_insn_reservation "ppc7450-ddiv" 35 + (and (eq_attr "type" "ddiv") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,fpu_7450*35") + +(define_insn_reservation "ppc7450-mfcr" 2 + (and (eq_attr "type" "mfcr,mtcr") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,mciu_7450") + +(define_insn_reservation "ppc7450-crlogical" 1 + (and (eq_attr "type" "cr_logical,delayed_cr") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,mciu_7450") + +(define_insn_reservation "ppc7450-mtjmpr" 2 + (and (eq_attr "type" "mtjmpr") + (eq_attr "cpu" "ppc7450")) + "nothing,mciu_7450*2") + +(define_insn_reservation "ppc7450-jmpreg" 1 + (and (eq_attr "type" "jmpreg,branch") + (eq_attr "cpu" "ppc7450")) + "nothing,bpu_7450") + +;; Altivec +(define_insn_reservation "ppc7450-vecsimple" 1 + (and (eq_attr "type" "vecsimple") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,ppc7450_vec_du,vecsmpl_7450") + +(define_insn_reservation "ppc7450-veccomplex" 4 + (and (eq_attr "type" "veccomplex") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,ppc7450_vec_du,veccmplx_7450") + +(define_insn_reservation "ppc7450-veccmp" 2 + (and (eq_attr "type" "veccmp") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,ppc7450_vec_du,veccmplx_7450") + +(define_insn_reservation "ppc7450-vecfloat" 4 + (and (eq_attr "type" "vecfloat") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,ppc7450_vec_du,vecflt_7450") + +(define_insn_reservation "ppc7450-vecperm" 2 + (and (eq_attr "type" "vecperm") + (eq_attr "cpu" "ppc7450")) + "ppc7450_du,ppc7450_vec_du,vecperm_7450") + |