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| author | Segher Boessenkool <segher@kernel.crashing.org> | 2014-05-08 00:00:58 +0200 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2014-05-08 00:00:58 +0200 |
| commit | d839f53b7dfd86250420bce15382c98cbd43b4ec (patch) | |
| tree | cd8a170e4a1bf065792be21e8461f7608f25a897 /gcc/config/rs6000/601.md | |
| parent | d3b4df0b173c3ad5f1e8f5d9f6a5df3518322129 (diff) | |
| download | gcc-d839f53b7dfd86250420bce15382c98cbd43b4ec.tar.gz | |
rs6000: New attributes for load/store: "sign_extend", "update" and "indexed"
The new attributes replace the instruction types *_ext*, *_u, *_ux.
This simplifies all code that does not care about the addressing modes,
putting the burden on the code that does care (mostly the scheduling
descriptions for certain CPUs).
It fixes a few minor bugs in the process.
The "update" and "indexed" attributes are automatic for any insn that
has a MEM as operand 0 or 1. Other insns have to set it manually, if
they do not like the default (which is "no"). Insns that are type
load/store/fpload/fpstore but have fewer than two operands need to set
it too, or the compiler will crash. There are very few of those.
This tries not to change semantics anywhere; in particular, the string
and multiple instructions set both "update" and "indexed" (although
they are neither).
From-SVN: r210190
Diffstat (limited to 'gcc/config/rs6000/601.md')
| -rw-r--r-- | gcc/config/rs6000/601.md | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/gcc/config/rs6000/601.md b/gcc/config/rs6000/601.md index d2f6825e569..94ba06cebcd 100644 --- a/gcc/config/rs6000/601.md +++ b/gcc/config/rs6000/601.md @@ -25,23 +25,22 @@ ;; PPC601 32-bit IU, FPU, BPU (define_insn_reservation "ppc601-load" 2 - (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ - load_l,store_c,sync") + (and (eq_attr "type" "load,load_l,store_c,sync") (eq_attr "cpu" "ppc601")) "iu_ppc601") (define_insn_reservation "ppc601-store" 2 - (and (eq_attr "type" "store,store_ux,store_u") + (and (eq_attr "type" "store") (eq_attr "cpu" "ppc601")) "iu_ppc601") (define_insn_reservation "ppc601-fpload" 3 - (and (eq_attr "type" "fpload,fpload_ux,fpload_u") + (and (eq_attr "type" "fpload") (eq_attr "cpu" "ppc601")) "iu_ppc601") (define_insn_reservation "ppc601-fpstore" 3 - (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") + (and (eq_attr "type" "fpstore") (eq_attr "cpu" "ppc601")) "iu_ppc601+fpu_ppc601") |