diff options
| author | danglin <danglin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2012-10-06 00:33:52 +0000 |
|---|---|---|
| committer | danglin <danglin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2012-10-06 00:33:52 +0000 |
| commit | 41445a29b8f8780dc7bdffef753a8c7f550250dc (patch) | |
| tree | 61caafb187cf21a3a14318b12ea2ebb5714ba75d /gcc/config/pa | |
| parent | 5cd1b1d3aaca0d8b55eb48c9c8634accdf759488 (diff) | |
| download | gcc-41445a29b8f8780dc7bdffef753a8c7f550250dc.tar.gz | |
PR rtl-optimization/54739
* config/pa/pa.md: Remove DImode and, not and, ior and xor patterns
for 32-bit targets. Adjust expanders.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@192152 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/pa')
| -rw-r--r-- | gcc/config/pa/pa.md | 60 |
1 files changed, 6 insertions, 54 deletions
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 4595357e9cb..80c40f5047a 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -5623,22 +5623,8 @@ [(set (match_operand:DI 0 "register_operand" "") (and:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "and_operand" "")))] - "" - " -{ - /* Both operands must be register operands. */ - if (!TARGET_64BIT && !register_operand (operands[2], DImode)) - FAIL; -}") - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (and:DI (match_operand:DI 1 "register_operand" "%r") - (match_operand:DI 2 "register_operand" "r")))] - "!TARGET_64BIT" - "and %1,%2,%0\;and %R1,%R2,%R0" - [(set_attr "type" "binary") - (set_attr "length" "8")]) + "TARGET_64BIT" + "") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,r") @@ -5664,15 +5650,6 @@ [(set (match_operand:DI 0 "register_operand" "=r") (and:DI (not:DI (match_operand:DI 1 "register_operand" "r")) (match_operand:DI 2 "register_operand" "r")))] - "!TARGET_64BIT" - "andcm %2,%1,%0\;andcm %R2,%R1,%R0" - [(set_attr "type" "binary") - (set_attr "length" "8")]) - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (and:DI (not:DI (match_operand:DI 1 "register_operand" "r")) - (match_operand:DI 2 "register_operand" "r")))] "TARGET_64BIT" "andcm %2,%1,%0" [(set_attr "type" "binary") @@ -5691,22 +5668,8 @@ [(set (match_operand:DI 0 "register_operand" "") (ior:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "reg_or_cint_ior_operand" "")))] - "" - " -{ - /* Both operands must be register operands. */ - if (!TARGET_64BIT && !register_operand (operands[2], DImode)) - FAIL; -}") - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (ior:DI (match_operand:DI 1 "register_operand" "%r") - (match_operand:DI 2 "register_operand" "r")))] - "!TARGET_64BIT" - "or %1,%2,%0\;or %R1,%R2,%R0" - [(set_attr "type" "binary") - (set_attr "length" "8")]) + "TARGET_64BIT" + "") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,r") @@ -5756,19 +5719,8 @@ [(set (match_operand:DI 0 "register_operand" "") (xor:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "register_operand" "")))] - "" - " -{ -}") - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (xor:DI (match_operand:DI 1 "register_operand" "%r") - (match_operand:DI 2 "register_operand" "r")))] - "!TARGET_64BIT" - "xor %1,%2,%0\;xor %R1,%R2,%R0" - [(set_attr "type" "binary") - (set_attr "length" "8")]) + "TARGET_64BIT" + "") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") |