* pa.md (7100lc, 7200, 7300 scheduling): Slightly refine

        handling of double precision multiplies.


        * pa.md (7100lc, 7200, 7300 scheduling): Refine handling of
        fpdiv and fpsqrt instructions.
        (7200 & 7300 scheduling): Fix typo in handling of
        store-load and store-store penalties.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@52946 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 24 insertions, 23 deletions

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index ca99b3249e2..2a6dea31660 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -327,7 +327,7 @@
 
 (define_automaton "pa7100lc")
 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
-(define_cpu_unit "fpalu_7100lc,fpdivsqrt_7100lc,fpmul_7100lc" "pa7100lc")
+(define_cpu_unit "fpalu_7100lc,fpmul_7100lc" "pa7100lc")
 (define_cpu_unit "mem_7100lc" "pa7100lc")
 
 (define_insn_reservation "Y0" 2
@@ -335,57 +335,58 @@
        (eq_attr "cpu" "7100LC,7200,7300"))
   "f_7100lc,fpalu_7100lc")
 
+;; Double precision multiplies lock the entire CPU for one
+;; cycle.  There is no way to avoid this lock and trying to
+;; schedule around the lock is pointless and thus there is no
+;; value in trying to model this lock.  Not modeling the lock
+;; allows for a smaller DFA and may reduce register pressure.
 (define_insn_reservation "Y1" 2
-  (and (eq_attr "type" "fpmulsgl")
+  (and (eq_attr "type" "fpmulsgl,fpmuldbl")
        (eq_attr "cpu" "7100LC,7200,7300"))
   "f_7100lc,fpmul_7100lc")
 
-(define_insn_reservation "Y2" 3
-  (and (eq_attr "type" "fpmuldbl")
-       (eq_attr "cpu" "7100LC,7200,7300"))
-  "f_7100lc,fpmul_7100lc,fpmul_7100lc")
-
-(define_insn_reservation "Y3" 8
-  (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
-       (eq_attr "cpu" "7100LC,7200,7300"))
-  "f_7100lc+fpdivsqrt_7100lc,fpdivsqrt_7100lc*7")
-
-(define_insn_reservation "Y4" 15
-  (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
+;; fp division and sqrt instructions lock the entire CPU for
+;; 7 cycles (single precision) or 14 cycles (double precision).
+;; There is no way to avoid this lock and trying to schedule
+;; around the lock is pointless and thus there is no value in
+;; trying to model this lock.  Not modeling the lock allows
+;; for a smaller DFA and may reduce register pressure.
+(define_insn_reservation "Y2" 1
+  (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
        (eq_attr "cpu" "7100LC,7200,7300"))
-  "f_7100lc+fpdivsqrt_7100lc,fpdivsqrt_7100lc*14")
+  "f_7100lc")
 
-(define_insn_reservation "Y5" 2
+(define_insn_reservation "Y3" 2
   (and (eq_attr "type" "load,fpload")
        (eq_attr "cpu" "7100LC,7200,7300"))
   "i1_7100lc+mem_7100lc")
 
-(define_insn_reservation "Y6" 2
+(define_insn_reservation "Y4" 2
   (and (eq_attr "type" "store,fpstore")
        (eq_attr "cpu" "7100LC"))
   "i1_7100lc+mem_7100lc,mem_7100lc")
 
-(define_insn_reservation "Y7" 1
+(define_insn_reservation "Y5" 1
   (and (eq_attr "type" "shift,nullshift")
        (eq_attr "cpu" "7100LC,7200,7300"))
   "i1_7100lc")
 
-(define_insn_reservation "Y8" 1
+(define_insn_reservation "Y6" 1
   (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
        (eq_attr "cpu" "7100LC,7200,7300"))
   "(i0_7100lc|i1_7100lc)")
 
 ;; The 7200 has a store-load penalty
-(define_insn_reservation "Y9" 2
+(define_insn_reservation "Y7" 2
   (and (eq_attr "type" "store,fpstore")
        (eq_attr "cpu" "7200"))
-  "i0_7100lc,mem_7100lc")
+  "i1_7100lc,mem_7100lc")
 
 ;; The 7300 has no penalty for store-store or store-load
-(define_insn_reservation "YA" 2
+(define_insn_reservation "Y8" 2
   (and (eq_attr "type" "store,fpstore")
        (eq_attr "cpu" "7300"))
-  "i0_7100lc")
+  "i1_7100lc")
 
 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
 ;; traditional architecture.