diff options
| author | danglin <danglin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2007-12-09 18:02:08 +0000 |
|---|---|---|
| committer | danglin <danglin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2007-12-09 18:02:08 +0000 |
| commit | 7050ff73578669785fb35072459803d2ecadc11d (patch) | |
| tree | 6c03efab36b85bc299f7ba354cfa23f643d60a6a /gcc/config/pa/pa64-regs.h | |
| parent | 1c79cc8c0c30803e49c4de328c802c118145d3e0 (diff) | |
| download | gcc-7050ff73578669785fb35072459803d2ecadc11d.tar.gz | |
PR middle-end/32889
PR target/34091
* pa.md: Consolidate HImode and QImode move patterns into one pattern
each, eliminating floating-point alternatives.
* pa-protos.h (pa_cannot_change_mode_class, pa_modes_tieable_p):
Declare functions.
* pa-64.h (SECONDARY_MEMORY_NEEDED): Define here.
* pa.c (pa_secondary_reload): Use an intermediate general register
for copies to/from floating-point register classes. Simplify code
SHIFT_REGS class. Provide additional comments.
(pa_cannot_change_mode_class, pa_modes_tieable_p): New functions.
* pa.h (MODES_TIEABLE_P): Use pa_modes_tieable_p.
(SECONDARY_MEMORY_NEEDED): Delete define.
(INT14_OK_STRICT): Define.
(MODE_OK_FOR_SCALED_INDEXING_P): Allow SFmode and DFmode when using
soft float.
(MODE_OK_FOR_UNSCALED_INDEXING_P): Likewise.
(GO_IF_LEGITIMATE_ADDRESS): Use INT14_OK_STRICT in REG+D case for
SFmode and DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Use INT14_OK_STRICT in mask selection.
Align DImode offsets when generating 64-bit code.
* pa32-regs.h (VALID_FP_MODE_P): Remove QImode and HImode.
(CANNOT_CHANGE_MODE_CLASS): Define.
* pa64-regs.h (VALID_FP_MODE_P): Remove QImode and HImode.
(CANNOT_CHANGE_MODE_CLASS): Define using pa_cannot_change_mode_class.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@130725 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/pa/pa64-regs.h')
| -rw-r--r-- | gcc/config/pa/pa64-regs.h | 16 |
1 files changed, 4 insertions, 12 deletions
diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h index ddc1f061ab2..828265f23b8 100644 --- a/gcc/config/pa/pa64-regs.h +++ b/gcc/config/pa/pa64-regs.h @@ -156,8 +156,7 @@ along with GCC; see the file COPYING3. If not see #define VALID_FP_MODE_P(MODE) \ ((MODE) == SFmode || (MODE) == DFmode \ || (MODE) == SCmode || (MODE) == DCmode \ - || (MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ - || (MODE) == DImode) + || (MODE) == SImode || (MODE) == DImode) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On the HP-PA, the cpu registers can hold any mode. We @@ -242,17 +241,10 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, {0x00000000, 0x10000000}, /* SHIFT_REGS */ \ {0xfffffffe, 0x1fffffff}} /* ALL_REGS */ -/* Defines invalid mode changes. +/* Defines invalid mode changes. */ - SImode loads to floating-point registers are not zero-extended. - The definition for LOAD_EXTEND_OP specifies that integer loads - narrower than BITS_PER_WORD will be zero-extended. As a result, - we inhibit changes from SImode unless they are to a mode that is - identical in size. */ - -#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ - ((FROM) == SImode && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ - ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ + pa_cannot_change_mode_class (FROM, TO, CLASS) /* Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression |