diff options
| author | danglin <danglin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-07-05 01:57:01 +0000 |
|---|---|---|
| committer | danglin <danglin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-07-05 01:57:01 +0000 |
| commit | 59ad801a2550282fa31d5aeb058fd10c8092a08d (patch) | |
| tree | ca9ac26e1b073140283691ca6509fb7b33a9d3fe /gcc/config/pa/pa64-regs.h | |
| parent | 9e3782eb7e2b94d08acfd7d7a9cacb60a8cc5b52 (diff) | |
| download | gcc-59ad801a2550282fa31d5aeb058fd10c8092a08d.tar.gz | |
PR target/21723
* pa.md: Remove fcpy alternative from movhi and movqi patterns.
* pa32-regs.h (HARD_REGNO_NREGS): Return two floating point registers
for complex modes when generating code for PA 1.0.
(VALID_FP_MODE_P): New macro.
(HARD_REGNO_MODE_OK): Use VALID_FP_MODE_P. Use non-overlapping register
sets for all general and floating point modes. Align wide floating
point modes to even register boundaries to comply with architectural
requirements.
(CLASS_MAX_NREGS): Update to align with change to HARD_REGNO_NREGS.
* pa64-regs.h (HARD_REGNO_NREGS): Update comment and formatting.
(VALID_FP_MODE_P): New macro.
(HARD_REGNO_MODE_OK): Use VALID_FP_MODE_P. Use non-overlapping register
sets for all general and floating point modes. Align wide floating
point modes to even register boundaries to comply with architectural
requirements.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@101613 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/pa/pa64-regs.h')
| -rw-r--r-- | gcc/config/pa/pa64-regs.h | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h index 65e594bef81..fe06c7771e0 100644 --- a/gcc/config/pa/pa64-regs.h +++ b/gcc/config/pa/pa64-regs.h @@ -145,11 +145,19 @@ Boston, MA 02110-1301, USA. */ This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. - For PA64, GPRs and FPRs hold 64 bits worth (we ignore the 32bit - addressability of the FPRs). i.e., we pretend each register holds - precisely WORD_SIZE bits. */ + For PA64, GPRs and FPRs hold 64 bits worth. We ignore the 32-bit + addressability of the FPRs and pretend each register holds precisely + WORD_SIZE bits. Note that SCmode values are placed in a single FPR. + Thus, any patterns defined to operate on these values would have to + use the 32-bit addressability of the FPR registers. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ - ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + +/* These are the valid FP modes. */ +#define VALID_FP_MODE_P(MODE) \ + ((MODE) == SFmode || (MODE) == DFmode \ + || (MODE) == SCmode || (MODE) == DCmode \ + || (MODE) == SImode || (MODE) == DImode) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On the HP-PA, the cpu registers can hold any mode. We @@ -158,8 +166,16 @@ Boston, MA 02110-1301, USA. */ ((REGNO) == 0 \ ? (MODE) == CCmode || (MODE) == CCFPmode \ /* Make wide modes be in aligned registers. */ \ + : FP_REGNO_P (REGNO) \ + ? (VALID_FP_MODE_P (MODE) \ + && (GET_MODE_SIZE (MODE) <= 8 \ + || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 1) == 0) \ + || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 3) == 0))) \ : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \ - || (GET_MODE_SIZE (MODE) <= 2 * UNITS_PER_WORD && ((REGNO) & 1) == 0))) + || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD \ + && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28)) \ + || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD \ + && ((REGNO) & 3) == 3 && (REGNO) <= 23))) /* How to renumber registers for dbx and gdb. |