summaryrefslogtreecommitdiff
path: root/gcc/config/pa/pa.md
diff options
context:
space:
mode:
authorJohn David Anglin <danglin@gcc.gnu.org>2019-05-24 23:12:16 +0000
committerJohn David Anglin <danglin@gcc.gnu.org>2019-05-24 23:12:16 +0000
commit0241901b0cd82e9d0ba06fa050dad3f051711eb4 (patch)
tree6739bb16d4dda32e1d6040649e91baa67f30a876 /gcc/config/pa/pa.md
parent6c7ae8c56f9341f180e097d5eb7ba05cb8eec413 (diff)
downloadgcc-0241901b0cd82e9d0ba06fa050dad3f051711eb4.tar.gz
re PR target/90530 (Invalid SUBREG insn generated by reload)
PR target/90530 * config/pa/pa.c (pa_can_change_mode_class): Accept mode changes from DImode to SImode in floating-point registers on 64-bit target. * config/pa/pa.md (umulsidi3): Change nonimmediate_operand to register_operand in xmpyu patterns. From-SVN: r271611
Diffstat (limited to 'gcc/config/pa/pa.md')
-rw-r--r--gcc/config/pa/pa.md8
1 files changed, 4 insertions, 4 deletions
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 1b4a5247370..8308b37461d 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5319,8 +5319,8 @@
(define_insn "umulsidi3"
[(set (match_operand:DI 0 "register_operand" "=f")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
- (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
+ (zero_extend:DI (match_operand:SI 2 "register_operand" "f"))))]
"TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
"xmpyu %1,%2,%0"
[(set_attr "type" "fpmuldbl")
@@ -5328,7 +5328,7 @@
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=f")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
(match_operand:DI 2 "uint32_operand" "f")))]
"TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
"xmpyu %1,%R2,%0"
@@ -5337,7 +5337,7 @@
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=f")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
(match_operand:DI 2 "uint32_operand" "f")))]
"TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
"xmpyu %1,%2R,%0"