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author | danglin <danglin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2009-08-20 01:36:11 +0000 |
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committer | danglin <danglin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2009-08-20 01:36:11 +0000 |
commit | 853940d980cdf01e6068fdf32ee64cf69704330b (patch) | |
tree | 962cbd2c93724b3b36ee41db76d0983c4e85960c /gcc/config/pa/pa.md | |
parent | 2a3d89a603c65d9f550aec27229a068c738fd302 (diff) | |
download | gcc-853940d980cdf01e6068fdf32ee64cf69704330b.tar.gz |
* pa.md (reload_inhi, reload_outhi, reload_inqi, reload_outqi): New
patterns.
* pa.c (emit_move_sequence): Check if address of operand1 is valid
for mode mode of operand0 when doing secondary reload for SAR.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@150951 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/pa/pa.md')
-rw-r--r-- | gcc/config/pa/pa.md | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index a20f406d347..20f64449097 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2740,6 +2740,40 @@ DONE; }") +;; Handle HImode input reloads requiring a general register as a +;; scratch register. +(define_expand "reload_inhi" + [(set (match_operand:HI 0 "register_operand" "=Z") + (match_operand:HI 1 "non_hard_reg_operand" "")) + (clobber (match_operand:HI 2 "register_operand" "=&r"))] + "" + " +{ + if (emit_move_sequence (operands, HImode, operands[2])) + DONE; + + /* We don't want the clobber emitted, so handle this ourselves. */ + emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); + DONE; +}") + +;; Handle HImode output reloads requiring a general register as a +;; scratch register. +(define_expand "reload_outhi" + [(set (match_operand:HI 0 "non_hard_reg_operand" "") + (match_operand:HI 1 "register_operand" "Z")) + (clobber (match_operand:HI 2 "register_operand" "=&r"))] + "" + " +{ + if (emit_move_sequence (operands, HImode, operands[2])) + DONE; + + /* We don't want the clobber emitted, so handle this ourselves. */ + emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); + DONE; +}") + (define_insn "" [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,r,r,Q,!*q,!r") @@ -2864,6 +2898,40 @@ DONE; }") +;; Handle QImode input reloads requiring a general register as a +;; scratch register. +(define_expand "reload_inqi" + [(set (match_operand:QI 0 "register_operand" "=Z") + (match_operand:QI 1 "non_hard_reg_operand" "")) + (clobber (match_operand:QI 2 "register_operand" "=&r"))] + "" + " +{ + if (emit_move_sequence (operands, QImode, operands[2])) + DONE; + + /* We don't want the clobber emitted, so handle this ourselves. */ + emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); + DONE; +}") + +;; Handle QImode output reloads requiring a general register as a +;; scratch register. +(define_expand "reload_outqi" + [(set (match_operand:QI 0 "non_hard_reg_operand" "") + (match_operand:QI 1 "register_operand" "Z")) + (clobber (match_operand:QI 2 "register_operand" "=&r"))] + "" + " +{ + if (emit_move_sequence (operands, QImode, operands[2])) + DONE; + + /* We don't want the clobber emitted, so handle this ourselves. */ + emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); + DONE; +}") + (define_insn "" [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,r,r,Q,!*q,!r") |