diff options
| author | danglin <danglin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-07-05 01:57:01 +0000 |
|---|---|---|
| committer | danglin <danglin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-07-05 01:57:01 +0000 |
| commit | 59ad801a2550282fa31d5aeb058fd10c8092a08d (patch) | |
| tree | ca9ac26e1b073140283691ca6509fb7b33a9d3fe /gcc/config/pa/pa.md | |
| parent | 9e3782eb7e2b94d08acfd7d7a9cacb60a8cc5b52 (diff) | |
| download | gcc-59ad801a2550282fa31d5aeb058fd10c8092a08d.tar.gz | |
PR target/21723
* pa.md: Remove fcpy alternative from movhi and movqi patterns.
* pa32-regs.h (HARD_REGNO_NREGS): Return two floating point registers
for complex modes when generating code for PA 1.0.
(VALID_FP_MODE_P): New macro.
(HARD_REGNO_MODE_OK): Use VALID_FP_MODE_P. Use non-overlapping register
sets for all general and floating point modes. Align wide floating
point modes to even register boundaries to comply with architectural
requirements.
(CLASS_MAX_NREGS): Update to align with change to HARD_REGNO_NREGS.
* pa64-regs.h (HARD_REGNO_NREGS): Update comment and formatting.
(VALID_FP_MODE_P): New macro.
(HARD_REGNO_MODE_OK): Use VALID_FP_MODE_P. Use non-overlapping register
sets for all general and floating point modes. Align wide floating
point modes to even register boundaries to comply with architectural
requirements.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@101613 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/pa/pa.md')
| -rw-r--r-- | gcc/config/pa/pa.md | 22 |
1 files changed, 10 insertions, 12 deletions
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index de5b75b022b..f724209c1e9 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2896,9 +2896,9 @@ (define_insn "" [(set (match_operand:HI 0 "move_dest_operand" - "=r,r,r,r,r,Q,!*q,!r,!*f") + "=r,r,r,r,r,Q,!*q,!r") (match_operand:HI 1 "move_src_operand" - "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))] + "r,J,N,K,RQ,rM,!rM,!*q"))] "register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode)" "@ @@ -2909,11 +2909,10 @@ ldh%M1 %1,%0 sth%M0 %r1,%0 mtsar %r1 - {mfctl|mfctl,w} %sar,%0 - fcpy,sgl %f1,%0" - [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu") + {mfctl|mfctl,w} %sar,%0" + [(set_attr "type" "move,move,move,shift,load,store,move,move") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4")]) (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") @@ -3021,9 +3020,9 @@ (define_insn "" [(set (match_operand:QI 0 "move_dest_operand" - "=r,r,r,r,r,Q,!*q,!r,!*f") + "=r,r,r,r,r,Q,!*q,!r") (match_operand:QI 1 "move_src_operand" - "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))] + "r,J,N,K,RQ,rM,!rM,!*q"))] "register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode)" "@ @@ -3034,11 +3033,10 @@ ldb%M1 %1,%0 stb%M0 %r1,%0 mtsar %r1 - {mfctl|mfctl,w} %%sar,%0 - fcpy,sgl %f1,%0" - [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu") + {mfctl|mfctl,w} %%sar,%0" + [(set_attr "type" "move,move,move,shift,load,store,move,move") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4")]) (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") |