2000-06-27 Philipp Thomas <pthomas@suse.de>

	* 1750a.h: Mark help strings for options/switches for translation.
	* a29k.h: Likewise.
	* alpha.h: Likewise.
	* arm.h: Likewise.
	* pe.h: Likewise.
	* riscix.h: Likewise.
	* c4x.h: Likewise.
	* clipper.h: Likewise.
	* convex.h: Likewise.
	* elxsi.h: Likewise.
	* fr30.h: Likewise.
	* fx80.h: Likewise.
	* h8300.h: Likewise.
	* i370.h: Likewise.
	* cygwin.h: Likewise.
	* dgux.h: Likewise.
	* djgpp.h: Likewise.
	* i386.h: Likewise.
	* osf1elf.h: Likewise.
	* osfrose.h: Likewise.
	* sco5.h: Likewise.
	* win32.h: Likewise.
	* i860.h: Likewise.
	* paragon.h: Likewise.
	* i960.h: Likewise.
	* ia64.h: Likewise.
	* m32r.h: Likewise.
	* mcore.h: Likewise.
	* mips.h: Likewise.
	* mn10300.h: Likewise.
	* ns32k.h: Likewise.
	* pdp11.h: Likewise.
	* pj.h: Likewise.
	* aix.h: Likewise.
	* aix41.h: Likewise.
	* aix43.h: Likewise.
	* beos.h: Likewise.
	* rs6000.h: Likewise.
	* sysv4.h: Likewise.
	* linux.h: Likewise.
	* linux64.h: Likewise.
	* sp64-elf.h: Likewise.
	* sparc.h: Likewise.
	* splet.h: Likewise.
	* v850.h: Likewise.
	* convex.h (TARGET_SWITCHES): Provide descriptions and mark them
	for translation.
	* sp86x-aout.h: Remove bogus first definition of SUBTARGET_SWITCHES.
	Properly document option and mark for translation.
	* sp86x-elf.h: Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@34724 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 24 insertions, 22 deletions

diff --git a/gcc/config/ns32k/ns32k.h b/gcc/config/ns32k/ns32k.h
index 4a0bf43d69d..352acaee639 100644
--- a/gcc/config/ns32k/ns32k.h
+++ b/gcc/config/ns32k/ns32k.h
@@ -99,28 +99,30 @@ extern int target_flags;
    where VALUE is the bits to set or minus the bits to clear.
    An empty string NAME is used to identify the default VALUE.  */
 
-#define TARGET_SWITCHES							      \
-  { { "32081", 1, "Use hardware fp"},					      \
-    { "soft-float", -257, "Don't use hardware fp"},			      \
-    { "rtd", 2, "Alternative calling convention"},			      \
-    { "nortd", -2, "Use normal calling convention"},			      \
-    { "regparm", 4, "Pass some arguments in registers"},		      \
-    { "noregparm", -4, "Pass all arguments on stack"},			      \
-    { "32532", 24, "Optimize for 32532 cpu"},				      \
-    { "32332", 16, "Optimize for 32332 cpu"},				      \
-    { "32332", -8, 0},							      \
-    { "32032", -24, "Optimize for 32032"},				      \
-    { "sb", -32, "Register sb is zero. Use for absolute addressing"},	      \
-    { "nosb", 32, "Do not use register sb"},				      \
-    { "bitfield", -64, "Do not use bitfield instructions"},		      \
-    { "nobitfield", 64, "Use bitfield instructions"},			      \
-    { "himem", 128, "Generate code for high memory"},			      \
-    { "nohimem", -128, "Generate code for low memory"},			      \
-    { "32381", 256, "32381 fpu"},					      \
-    { "mult-add", 512, "Use multiply-accumulate fp instructions"},	      \
-    { "nomult-add", -512, "Do not use multiply-accumulate fp instructions" }, \
-    { "src", 1024, "\"Small register classes\" kludge"},		      \
-    { "nosrc", -1024, "No \"Small register classes\" kludge"},		      \
+#define TARGET_SWITCHES							\
+  { { "32081", 1, N_("Use hardware fp")},				\
+    { "soft-float", -257, N_("Don't use hardware fp")},			\
+    { "rtd", 2, N_("Alternative calling convention")},			\
+    { "nortd", -2, N_("Use normal calling convention")},		\
+    { "regparm", 4, N_("Pass some arguments in registers")},		\
+    { "noregparm", -4, N_("Pass all arguments on stack")},		\
+    { "32532", 24, N_("Optimize for 32532 cpu")},			\
+    { "32332", 16, N_("Optimize for 32332 cpu")},			\
+    { "32332", -8, 0},							\
+    { "32032", -24, N_("Optimize for 32032")},				\
+    { "sb", -32,							\
+      N_("Register sb is zero. Use for absolute addressing")},		\
+    { "nosb", 32, N_("Do not use register sb")},			\
+    { "bitfield", -64, N_("Do not use bitfield instructions")},		\
+    { "nobitfield", 64, N_("Use bitfield instructions")},		\
+    { "himem", 128, N_("Generate code for high memory")},		\
+    { "nohimem", -128, N_("Generate code for low memory")},		\
+    { "32381", 256, N_("32381 fpu")},					\
+    { "mult-add", 512, N_("Use multiply-accumulate fp instructions")},	\
+    { "nomult-add", -512,						\
+      N_("Do not use multiply-accumulate fp instructions") }, 		\
+    { "src", 1024, N_("\"Small register classes\" kludge")},		\
+    { "nosrc", -1024, N_("No \"Small register classes\" kludge")},	\
     { "", TARGET_DEFAULT, 0}}
 
 /* TARGET_DEFAULT is defined in encore.h, pc532.h, etc.  */