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author | sje <sje@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-03-25 23:12:01 +0000 |
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committer | sje <sje@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-03-25 23:12:01 +0000 |
commit | 14844884d52bbf500a4c55ff7233b6b5ab094443 (patch) | |
tree | 8840e5195460da8bebf3f6b8d770f613ca1e5b0a /gcc/config/mips | |
parent | 4688e4d0423273253a5280b9625c9fb7d21f422f (diff) | |
download | gcc-14844884d52bbf500a4c55ff7233b6b5ab094443.tar.gz |
2013-03-25 Steve Ellcey <sellcey@mips.com>
* config/mips/mmips-cpus.def (74kc, 74kf2_1, 74kf, 74kf, 74kf1_1,
74kfx, 74kx, 74kf3_2): Add PTF_AVOID_IMADD.
* config/mips/mips.c (mips_option_override): Set IMADD default.
* config/mips/mips.h (PTF_AVOID_IMADD): New.
(ISA_HAS_MADD_MSUB): Remove MIPS16 check.
(GENERATE_MADD_MSUB): Remove TUNE_74K check, add MIPS16 check.
* config/mips/mips.md (mimadd): New flag for integer madd/msub.
* doc/invoke.texi (-mimadd/-mno-imadd): New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@197072 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/mips')
-rw-r--r-- | gcc/config/mips/mips-cpus.def | 14 | ||||
-rw-r--r-- | gcc/config/mips/mips.c | 15 | ||||
-rw-r--r-- | gcc/config/mips/mips.h | 22 | ||||
-rw-r--r-- | gcc/config/mips/mips.opt | 4 |
4 files changed, 40 insertions, 15 deletions
diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 1cc19999373..9e5fd162189 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -121,13 +121,13 @@ MIPS_CPU ("34kfx", PROCESSOR_24KF1_1, 33, 0) MIPS_CPU ("34kx", PROCESSOR_24KF1_1, 33, 0) MIPS_CPU ("34kn", PROCESSOR_24KC, 33, 0) /* 34K with MT but no DSP. */ -MIPS_CPU ("74kc", PROCESSOR_74KC, 33, 0) /* 74K with DSPr2. */ -MIPS_CPU ("74kf2_1", PROCESSOR_74KF2_1, 33, 0) -MIPS_CPU ("74kf", PROCESSOR_74KF2_1, 33, 0) -MIPS_CPU ("74kf1_1", PROCESSOR_74KF1_1, 33, 0) -MIPS_CPU ("74kfx", PROCESSOR_74KF1_1, 33, 0) -MIPS_CPU ("74kx", PROCESSOR_74KF1_1, 33, 0) -MIPS_CPU ("74kf3_2", PROCESSOR_74KF3_2, 33, 0) +MIPS_CPU ("74kc", PROCESSOR_74KC, 33, PTF_AVOID_IMADD) /* 74K with DSPr2. */ +MIPS_CPU ("74kf2_1", PROCESSOR_74KF2_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kf", PROCESSOR_74KF2_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kf1_1", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kfx", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kx", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kf3_2", PROCESSOR_74KF3_2, 33, PTF_AVOID_IMADD) MIPS_CPU ("1004kc", PROCESSOR_24KC, 33, 0) /* 1004K with MT/DSP. */ MIPS_CPU ("1004kf2_1", PROCESSOR_24KF2_1, 33, 0) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 4957a150078..d7a0749b4ee 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -16912,6 +16912,21 @@ mips_option_override (void) warning (0, "the %qs architecture does not support branch-likely" " instructions", mips_arch_info->name); + /* If the user hasn't specified -mimadd or -mno-imadd set + MASK_IMADD based on the target architecture and tuning + flags. */ + if ((target_flags_explicit & MASK_IMADD) == 0) + { + if (ISA_HAS_MADD_MSUB && + (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0) + target_flags |= MASK_IMADD; + else + target_flags &= ~MASK_IMADD; + } + else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB) + warning (0, "the %qs architecture does not support madd or msub" + " instructions", mips_arch_info->name); + /* The effect of -mabicalls isn't defined for the EABI. */ if (mips_abi == ABI_EABI && TARGET_ABICALLS) { diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 0db36988dcc..dd694f30e5c 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -47,8 +47,15 @@ extern int target_flags_explicit; PTF_AVOID_BRANCHLIKELY Set if it is usually not profitable to use branch-likely instructions for this target, typically because the branches are always predicted - taken and so incur a large overhead when not taken. */ -#define PTF_AVOID_BRANCHLIKELY 0x1 + taken and so incur a large overhead when not taken. + + PTF_AVOID_IMADD + Set if it is usually not profitable to use the integer MADD or MSUB + instructions because of the overhead of getting the result out of + the HI/LO registers. */ + +#define PTF_AVOID_BRANCHLIKELY 0x1 +#define PTF_AVOID_IMADD 0x2 /* Information about one recognized processor. Defined here for the benefit of TARGET_CPU_CPP_BUILTINS. */ @@ -874,14 +881,13 @@ struct mips_cpu_info { && !TARGET_MIPS16) /* ISA has integer multiply-accumulate instructions, madd and msub. */ -#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \ - || ISA_MIPS32R2 \ - || ISA_MIPS64 \ - || ISA_MIPS64R2) \ - && !TARGET_MIPS16) +#define ISA_HAS_MADD_MSUB (ISA_MIPS32 \ + || ISA_MIPS32R2 \ + || ISA_MIPS64 \ + || ISA_MIPS64R2) /* Integer multiply-accumulate instructions should be generated. */ -#define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K) +#define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */ #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4 diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index f9e88b3cd72..e11710db3c0 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -58,6 +58,10 @@ mmad Target Report Var(TARGET_MAD) Use PMC-style 'mad' instructions +mimadd +Target Report Mask(IMADD) +Use integer madd/msub instructions + march= Target RejectNegative Joined Var(mips_arch_option) ToLower Enum(mips_arch_opt_value) -march=ISA Generate code for the given ISA |