* config/m32c/bitops.md, config/m32c/jump.md,

	config/m32c/m32c.c, config/m32c/m32c.h, config/m32r/m32r.c,
	config/m32r/m32r.h, config/m32r/m32r.md,
	config/m32r/predicates.md, config/m68hc11/larith.asm,
	config/m68hc11/m68hc11.c, config/m68hc11/m68hc11.h,
	config/m68k/m68k.h, config/mcore/mcore.md, config/mips/4k.md,
	config/mips/mips-protos.h, config/mips/mips.c,
	config/mips/mips.h, config/mips/mips.md, config/mips/mips16.S,
	config/mn10300/mn10300.h, config/mn10300/predicates.md,
	config/mt/mt.c, config/mt/mt.h, config/mt/mt.md: Follow
	spelling conventions.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@121565 138bc75d-0d04-0410-961f-82ee72b054a4

6 files changed, 42 insertions, 42 deletions

diff --git a/gcc/config/mips/4k.md b/gcc/config/mips/4k.md
index 6f7d6d1d979..8e660934ef8 100644
--- a/gcc/config/mips/4k.md
+++ b/gcc/config/mips/4k.md
@@ -51,8 +51,8 @@
   "r4k_ixu_arith")
 
 ;; 4Kc/4Km 
-;; unsigned divide - 8/16/24/32 bit operand have latencies  9/17/25/33
-;;   signed divide - 8/16/24/32 bit operand have latencies 10/18/26/34
+;; unsigned divide - 8/16/24/32-bit operand have latencies  9/17/25/33
+;;   signed divide - 8/16/24/32-bit operand have latencies 10/18/26/34
 (define_insn_reservation "r4k_idiv_4kc" 34
   (and (eq_attr "cpu" "4kc")
        (and (eq_attr "type" "idiv")
diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index e5716da4d03..a9fa42ee815 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -3,7 +3,7 @@
    1999, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
    Contributed by A. Lichnewsky (lich@inria.inria.fr).
    Changed by Michael Meissner	(meissner@osf.org).
-   64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
+   64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
    Brendan Eich (brendan@microunity.com).
 
 This file is part of GCC.
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 1f8a56c057a..93c482368ae 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -3,7 +3,7 @@
    1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
    Contributed by A. Lichnewsky, lich@inria.inria.fr.
    Changes by Michael Meissner, meissner@osf.org.
-   64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
+   64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
    Brendan Eich, brendan@microunity.com.
 
 This file is part of GCC.
@@ -2522,7 +2522,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
 	      return true;
 	    }
 
-	  /* We can use cmpi for an xor with an unsigned 16 bit value.  */
+	  /* We can use cmpi for an xor with an unsigned 16-bit value.  */
 	  if ((outer_code) == XOR
 	      && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
 	    {
@@ -2531,7 +2531,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
 	    }
 
 	  /* We may be able to use slt or sltu for a comparison with a
-	     signed 16 bit value.  (The boundary conditions aren't quite
+	     signed 16-bit value.  (The boundary conditions aren't quite
 	     right, but this is just a heuristic anyhow.)  */
 	  if (((outer_code) == LT || (outer_code) == LE
 	       || (outer_code) == GE || (outer_code) == GT
@@ -2706,7 +2706,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
       return true;
 
     case SIGN_EXTEND:
-      /* A sign extend from SImode to DImode in 64 bit mode is often
+      /* A sign extend from SImode to DImode in 64-bit mode is often
          zero instructions, because the result can often be used
          directly by another instruction; we'll call it one.  */
       if (TARGET_64BIT && mode == DImode
@@ -2960,7 +2960,7 @@ mips_output_move (rtx dest, rtx src)
       if (src_code == CONST_INT)
 	{
 	  /* Don't use the X format, because that will give out of
-	     range numbers for 64 bit hosts and 32 bit targets.  */
+	     range numbers for 64-bit hosts and 32-bit targets.  */
 	  if (!TARGET_MIPS16)
 	    return "li\t%0,%1\t\t\t# %X1";
 
@@ -3888,8 +3888,8 @@ function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
       && host_integerp (TYPE_SIZE_UNIT (type), 1)
       && named)
     {
-      /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
-	 structure contains a double in its entirety, then that 64 bit
+      /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
+	 structure contains a double in its entirety, then that 64-bit
 	 chunk is passed in a floating point register.  */
       tree field;
 
@@ -3905,7 +3905,7 @@ function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
       if (field != 0)
 	{
 	  /* Now handle the special case by returning a PARALLEL
-	     indicating where each 64 bit chunk goes.  INFO.REG_WORDS
+	     indicating where each 64-bit chunk goes.  INFO.REG_WORDS
 	     chunks are passed in registers.  */
 	  unsigned int i;
 	  HOST_WIDE_INT bitpos;
@@ -6541,7 +6541,7 @@ mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
 
   /* Save registers starting from high to low.  The debuggers prefer at least
      the return register be stored at func+4, and also it allows us not to
-     need a nop in the epilog if at least one register is reloaded in
+     need a nop in the epilogue if at least one register is reloaded in
      addition to return address.  */
   offset = cfun->machine->frame.gp_sp_offset - sp_offset;
   for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
@@ -6645,8 +6645,8 @@ mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
 #endif
 
   /* In mips16 mode, we may need to generate a 32 bit to handle
-     floating point arguments.  The linker will arrange for any 32 bit
-     functions to call this stub, which will then jump to the 16 bit
+     floating point arguments.  The linker will arrange for any 32-bit
+     functions to call this stub, which will then jump to the 16-bit
      function proper.  */
   if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
       && current_function_args_info.fp_code != 0)
@@ -7895,7 +7895,7 @@ mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
   int gparg, fparg;
   unsigned int f;
 
-  /* This code only works for the original 32 bit ABI and the O64 ABI.  */
+  /* This code only works for the original 32-bit ABI and the O64 ABI.  */
   gcc_assert (TARGET_OLDABI);
 
   if (from_fp_p)
@@ -7943,9 +7943,9 @@ mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
 }
 
 /* Build a mips16 function stub.  This is used for functions which
-   take arguments in the floating point registers.  It is 32 bit code
+   take arguments in the floating point registers.  It is 32-bit code
    that moves the floating point args into the general registers, and
-   then jumps to the 16 bit code.  */
+   then jumps to the 16-bit code.  */
 
 static void
 build_mips16_function_stub (FILE *file)
@@ -8040,11 +8040,11 @@ static struct mips16_stub *mips16_stubs;
 
 /* Build a call stub for a mips16 call.  A stub is needed if we are
    passing any floating point values which should go into the floating
-   point registers.  If we are, and the call turns out to be to a 32
-   bit function, the stub will be used to move the values into the
-   floating point registers before calling the 32 bit function.  The
-   linker will magically adjust the function call to either the 16 bit
-   function or the 32 bit stub, depending upon where the function call
+   point registers.  If we are, and the call turns out to be to a
+   32-bit function, the stub will be used to move the values into the
+   floating point registers before calling the 32-bit function.  The
+   linker will magically adjust the function call to either the 16-bit
+   function or the 32-bit stub, depending upon where the function call
    is actually defined.
 
    Similarly, we need a stub if the return value might come back in a
@@ -8164,7 +8164,7 @@ build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
     {
       /* Build a special purpose stub.  When the linker sees a
 	 function call in mips16 code, it will check where the target
-	 is defined.  If the target is a 32 bit call, the linker will
+	 is defined.  If the target is a 32-bit call, the linker will
 	 search for the section defined here.  It can tell which
 	 symbol this section is associated with by looking at the
 	 relocation information (the name is unreliable, since this
@@ -8223,7 +8223,7 @@ build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
 	}
 
       /* We build the stub code by hand.  That's the only way we can
-	 do it, since we can't generate 32 bit code during a 16 bit
+	 do it, since we can't generate 32-bit code during a 16-bit
 	 compilation.  */
 
       /* We don't want the assembler to insert any nops here.  */
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index f01349bb0db..de926be4fd8 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -3,7 +3,7 @@
    1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
    Contributed by A. Lichnewsky (lich@inria.inria.fr).
    Changed by Michael Meissner	(meissner@osf.org).
-   64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
+   64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
    Brendan Eich (brendan@microunity.com).
 
 This file is part of GCC.
@@ -83,7 +83,7 @@ struct mips_rtx_cost_data
 
 /* Which ABI to use.  ABI_32 (original 32, or o32), ABI_N32 (n32),
    ABI_64 (n64) are all defined by SGI.  ABI_O64 is o32 extended
-   to work on a 64 bit machine.  */
+   to work on a 64-bit machine.  */
 
 #define ABI_32  0
 #define ABI_N32 1
@@ -96,7 +96,7 @@ struct mips_rtx_cost_data
 struct mips_cpu_info {
   /* The 'canonical' name of the processor as far as GCC is concerned.
      It's typically a manufacturer's prefix followed by a numerical
-     designation.  It should be lower case.  */
+     designation.  It should be lowercase.  */
   const char *name;
 
   /* The internal processor number that most closely matches this
@@ -566,7 +566,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
    ABI for which this is true.  */
 #define ABI_HAS_64BIT_SYMBOLS	(mips_abi == ABI_64 && !TARGET_SYM32)
 
-/* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3).  */
+/* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3).  */
 #define ISA_HAS_64BIT_REGS	(ISA_MIPS3				\
 				 || ISA_MIPS4				\
 				 || ISA_MIPS64)
@@ -704,7 +704,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
 #define ISA_HAS_EXT_INS		(ISA_MIPS32R2				\
 				 && !TARGET_MIPS16)
 
-/* ISA has instructions for accessing top part of 64 bit fp regs */
+/* ISA has instructions for accessing top part of 64-bit fp regs.  */
 #define ISA_HAS_MXHC1		(TARGET_FLOAT64 && ISA_MIPS32R2)
 
 /* True if the result of a load is not available to the next instruction.
@@ -1123,7 +1123,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
    on the full register even if a narrower mode is specified.  */
 #define WORD_REGISTER_OPERATIONS
 
-/* When in 64 bit mode, move insns will sign extend SImode and CCmode
+/* When in 64-bit mode, move insns will sign extend SImode and CCmode
    moves.  All other references are zero extended.  */
 #define LOAD_EXTEND_OP(MODE) \
   (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
@@ -1893,8 +1893,8 @@ typedef struct mips_args {
 
   /* On the mips16, we need to keep track of which floating point
      arguments were passed in general registers, but would have been
-     passed in the FP regs if this were a 32 bit function, so that we
-     can move them to the FP regs if we wind up calling a 32 bit
+     passed in the FP regs if this were a 32-bit function, so that we
+     can move them to the FP regs if we wind up calling a 32-bit
      function.  We record this information in fp_code, encoded in base
      four.  A zero digit means no floating point argument, a one digit
      means an SFmode argument, and a two digit means a DFmode argument,
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index b175fb343e8..a14b449a11d 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -3,7 +3,7 @@
 ;;  1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
 ;;  Contributed by   A. Lichnewsky, lich@inria.inria.fr
 ;;  Changes by       Michael Meissner, meissner@osf.org
-;;  64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
+;;  64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
 ;;  Brendan Eich, brendan@microunity.com.
 
 ;; This file is part of GCC.
@@ -1699,8 +1699,8 @@
   [(set_attr "type" "imul")
    (set_attr "mode" "DI")])
 
-;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
-;; instruction.  The HI/LO registers are used as a 64 bit accumulator.
+;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
+;; instruction.  The HI/LO registers are used as a 64-bit accumulator.
 
 (define_insn "madsi"
   [(set (match_operand:SI 0 "register_operand" "+l")
@@ -3533,8 +3533,8 @@
 ;; the sum of two general registers.  We use two versions for each of
 ;; these four instructions: one where the two general registers are
 ;; SImode, and one where they are DImode.  This is because general
-;; registers will be in SImode when they hold 32 bit values, but,
-;; since the 32 bit values are always sign extended, the [ls][wd]xc1
+;; registers will be in SImode when they hold 32-bit values, but,
+;; since the 32-bit values are always sign extended, the [ls][wd]xc1
 ;; instructions will still work correctly.
 
 ;; ??? Perhaps it would be better to support these instructions by
diff --git a/gcc/config/mips/mips16.S b/gcc/config/mips/mips16.S
index a6afa0c0544..5894a862f5c 100644
--- a/gcc/config/mips/mips16.S
+++ b/gcc/config/mips/mips16.S
@@ -38,7 +38,7 @@ Boston, MA 02110-1301, USA.  */
    values using the soft-float calling convention, but do the actual
    operation using the hard floating point instructions.  */
 
-/* This file contains 32 bit assembly code.  */
+/* This file contains 32-bit assembly code.  */
 	.set nomips16
 
 /* Start a function.  */
@@ -185,8 +185,8 @@ STARTFN (__mips16_fix_truncsfsi)
 /* The double precision operations.  We need to use different code
    based on the preprocessor symbol __mips64, because the way in which
    double precision values will change.  Without __mips64, the value
-   is passed in two 32 bit registers.  With __mips64, the value is
-   passed in a single 64 bit register.  */
+   is passed in two 32-bit registers.  With __mips64, the value is
+   passed in a single 64-bit register.  */
 
 /* Load the first double precision operand.  */
 
@@ -425,7 +425,7 @@ STARTFN (__mips16_ret_df)
 #endif
 #endif /* !__mips_single_float */
 
-/* These functions are used by 16 bit code when calling via a function
+/* These functions are used by 16-bit code when calling via a function
    pointer.  They must copy the floating point arguments from the gp
    regs into the fp regs.  The function to call will be in $2.  The
    exact set of floating point arguments to copy is encoded in the
@@ -511,7 +511,7 @@ STARTFN (__mips16_call_stub_10)
    to use it to hold the return address.
 
    Note that we do not know whether the function we are calling is 16
-   bit or 32 bit.  However, it does not matter, because 16 bit
+   bit or 32 bit.  However, it does not matter, because 16-bit
    functions always return floating point values in both the gp and
    the fp regs.  It would be possible to check whether the function
    being called is 16 bits, in which case the copy is unnecessary;