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authorrsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4>2005-05-11 12:52:58 +0000
committerrsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4>2005-05-11 12:52:58 +0000
commit9e3acd0d030d6bda37fb26139656c9aeb83ee659 (patch)
tree38c6d6aa2e12cfcfadb23595bfdc50ba84dbd6b7 /gcc/config/mips/sb1.md
parent23325b336bf95d02c81b57fabe142ae13a3cae2b (diff)
downloadgcc-9e3acd0d030d6bda37fb26139656c9aeb83ee659.tar.gz
* config/mips/mips.md (type): Add imul3.
(length, hazard, may_clobber_hilo): Check for imul3. (mulsi3_mult3, muldi3_mult3, *muls, <su>mulsi3_highpart_mulhi_internal) (*<su>mulsi3_highpart_neg_mulhi_internal): Set attr to imul3. * config/mips/24k.md (r24k_int_mul3): Enable this reservation for a 3 operand mul and its bypasses. * config/mips/3000.md (r3k_imul): Add imul3 to reservations. * config/mips/4000.md (r4k_imul): Likewise. * config/mips/4100.md (r4100_imul_si, r4100_imul_di): Likewise. * config/mips/4130.md (vr4130_class, vr4130_mulsi) (vr4130_muldi): Likewise. * config/mips/4300.md (r4300_imul_si, r4300_imul_di): Likewise. * config/mips/4600.md (r4600_imul, r4650_imul): Likewise. * config/mips/5000.md (r5k_imul_si, r5k_imul_di): Likewise. * config/mips/5400.md (ir_vr54_imul_si, ir_vr54_imul_di) (ir_vr54_imadd_si): Likewise. * config/mips/5500.md (ir_vr55_imul_si, ir_vr55_imul_di): Likewise. * config/mips/7000.md (rm7_impy_si_mult, rm7_impy_si_mul) (rm7_impy_di): Likewise. * config/mips/9000.md (rm9k_mulsi, rm9k_muldi): Likewise. * config/mips/generic.md (generic_imul): Likewise. * config/mips/sb1.md (ir_sb1_mulsi, ir_sb1_muldi): Likewise. * config/mips/sr71k.md (ir_sr70_imul_si, ir_sr70_imul_di): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@99577 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/mips/sb1.md')
-rw-r--r--gcc/config/mips/sb1.md4
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/mips/sb1.md b/gcc/config/mips/sb1.md
index 3ab033302fd..b1b085f45ed 100644
--- a/gcc/config/mips/sb1.md
+++ b/gcc/config/mips/sb1.md
@@ -296,7 +296,7 @@
(define_insn_reservation "ir_sb1_mulsi" 3
(and (eq_attr "cpu" "sb1")
- (and (eq_attr "type" "imul,imadd")
+ (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "SI")))
"sb1_ex1+sb1_mul")
@@ -305,7 +305,7 @@
(define_insn_reservation "ir_sb1_muldi" 4
(and (eq_attr "cpu" "sb1")
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "DI")))
"sb1_ex1+sb1_mul, sb1_mul")