diff options
| author | echristo <echristo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2002-04-10 03:40:00 +0000 |
|---|---|---|
| committer | echristo <echristo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2002-04-10 03:40:00 +0000 |
| commit | a87d8cb5071e60e984ed60e995fd0f025ca996a5 (patch) | |
| tree | 0ec004e3c4961b9c4fda3c7a8bc66bd90915255f /gcc/config/mips/mips.h | |
| parent | e701a4778f1ee1c5177bdaf3f7f17e5304426d6d (diff) | |
| download | gcc-a87d8cb5071e60e984ed60e995fd0f025ca996a5.tar.gz | |
2002-04-09 Eric Christopher <echristo@redhat.com>
* config/mips/mips.h (ASM_OUTPUT_ALIGNED_DECL_COMMON): Add additional
information to .comm directive.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@52109 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/mips/mips.h')
| -rw-r--r-- | gcc/config/mips/mips.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 976f0b7543f..6db24f4dd3e 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -2311,7 +2311,7 @@ extern enum reg_class mips_char_to_class[256]; memory and loading that memory location into a register of CLASS2. Do not define this macro if its value would always be zero. */ - +#if 0 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ ((!TARGET_DEBUG_H_MODE \ && GET_MODE_CLASS (MODE) == MODE_INT \ @@ -2320,7 +2320,7 @@ extern enum reg_class mips_char_to_class[256]; || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \ && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \ || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS)))) - +#endif /* The HI and LO registers can only be reloaded via the general registers. Condition code registers can only be loaded to the general registers, and from the floating point registers. */ @@ -4485,8 +4485,11 @@ while (0) (SIZE)); \ } \ else \ - mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \ + { \ + mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u", \ (SIZE)); \ + fprintf ((STREAM), "%u\n", ((unsigned)(ALIGN) / BITS_PER_UNIT));\ + } \ } while (0) |