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authorhp <hp@138bc75d-0d04-0410-961f-82ee72b054a4>2000-09-25 10:01:10 +0000
committerhp <hp@138bc75d-0d04-0410-961f-82ee72b054a4>2000-09-25 10:01:10 +0000
commit1495af193531f252f28d653b5fdc6edfcd7d2253 (patch)
tree1bc96d2392cbae97ded863de5c4e79d19b5508b4 /gcc/config/mips/iris6.h
parentabfc02622abb5bb491af815769fea2edb4b5344e (diff)
downloadgcc-1495af193531f252f28d653b5fdc6edfcd7d2253.tar.gz
definitions in config/m[ci]*:
Changes add TABs on either or both sides, covering start of line, up to any operand for all .*ASM.*_OP definitions. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@36610 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/mips/iris6.h')
-rw-r--r--gcc/config/mips/iris6.h26
1 files changed, 13 insertions, 13 deletions
diff --git a/gcc/config/mips/iris6.h b/gcc/config/mips/iris6.h
index 2b66e4ae109..3c92998d1c9 100644
--- a/gcc/config/mips/iris6.h
+++ b/gcc/config/mips/iris6.h
@@ -1,5 +1,5 @@
/* Definitions of target machine for GNU compiler. Iris version 6.
- Copyright (C) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
+ Copyright (C) 1994, 1995, 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
This file is part of GNU CC.
@@ -185,8 +185,8 @@ Boston, MA 02111-1307, USA. */
/* Define the strings used for the special svr4 .type and .size directives. */
-#define TYPE_ASM_OP ".type"
-#define SIZE_ASM_OP ".size"
+#define TYPE_ASM_OP "\t.type\t"
+#define SIZE_ASM_OP "\t.size\t"
/* This is how we tell the assembler that a symbol is weak. */
@@ -205,7 +205,7 @@ Boston, MA 02111-1307, USA. */
#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0)
-#define POPSECTION_ASM_OP ".popsection"
+#define POPSECTION_ASM_OP "\t.popsection"
#define DEBUG_INFO_SECTION ".debug_info,0x7000001e,0,0,1"
#define DEBUG_LINE_SECTION ".debug_line,0x7000001e,0,0,1"
@@ -250,9 +250,9 @@ Boston, MA 02111-1307, USA. */
and dtor lists this way, so we use -init and -fini to invoke the
do_global_* functions instead of running collect2. */
-#define BSS_SECTION_ASM_OP ".section\t.bss"
+#define BSS_SECTION_ASM_OP "\t.section\t.bss"
#define CONST_SECTION_ASM_OP_32 "\t.rdata"
-#define CONST_SECTION_ASM_OP_64 ".section\t.rodata"
+#define CONST_SECTION_ASM_OP_64 "\t.section\t.rodata"
/* The IRIX 6 assembler .section directive takes four additional args:
section type, flags, entry size, and alignment. The alignment of the
@@ -263,25 +263,25 @@ Boston, MA 02111-1307, USA. */
/* If we are included from crtstuff.c, these need to be plain strings.
_MIPS_SZPTR is defined in SUBTARGET_CPP_SPEC above. */
#if _MIPS_SZPTR == 64
-#define CTORS_SECTION_ASM_OP ".section\t.ctors,1,2,0,8"
-#define DTORS_SECTION_ASM_OP ".section\t.dtors,1,2,0,8"
+#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,1,2,0,8"
+#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,1,2,0,8"
#else /* _MIPS_SZPTR != 64 */
-#define CTORS_SECTION_ASM_OP ".section\t.ctors,1,2,0,4"
-#define DTORS_SECTION_ASM_OP ".section\t.dtors,1,2,0,4"
+#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,1,2,0,4"
+#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,1,2,0,4"
#endif /* _MIPS_SZPTR == 64 */
#else /* ! (defined (CRT_BEGIN) || defined (CRT_END)) */
/* If we are included from varasm.c, these need to depend on -mabi. */
#define CTORS_SECTION_ASM_OP \
- (Pmode == DImode ? ".section\t.ctors,1,2,0,8" : ".section\t.ctors,1,2,0,4")
+ (Pmode == DImode ? "\t.section\t.ctors,1,2,0,8" : "\t.section\t.ctors,1,2,0,4")
#define DTORS_SECTION_ASM_OP \
- (Pmode == DImode ? ".section\t.dtors,1,2,0,8" : ".section\t.dtors,1,2,0,4")
+ (Pmode == DImode ? "\t.section\t.dtors,1,2,0,8" : "\t.section\t.dtors,1,2,0,4")
#endif /* defined (CRT_BEGIN) || defined (CRT_END) */
/* dwarf2out will handle padding this data properly. We definitely don't
want it 8-byte aligned on n32. */
-#define EH_FRAME_SECTION_ASM_OP ".section\t.eh_frame,1,2,0,1"
+#define EH_FRAME_SECTION_ASM_OP "\t.section\t.eh_frame,1,2,0,1"
/* A default list of other sections which we might be "in" at any given
time. For targets that use additional sections (e.g. .tdesc) you