gcc/

2007-07-03  Richard Sandiford  <richard@codesourcery.com>
	    David Ung  <davidu@mips.com>

	* doc/invoke.texi: Replace -march=24kf with -march=24kf2_1 and
	-march=24kx with -march=24kf1_1.  Likewise 24ke[fx], 34k[fx]
	and 74k[fx].  Document aliases for the new options.
	* config/mips/mips.h (PROCESSOR_24KF): Rename to...
	(PROCESSOR_24KF2_1): ...this.
	(PROCESSOR_24KX): Rename to...
	(PROCESSOR_24KF1_1): ...this.
	(PROCESSOR_74KF): Rename to...
	(PROCESSOR_74KF2_1): ...this.
	(PROCESSOR_74KX): Rename to...
	(PROCESSOR_74KF1_1): ...this.
	(TUNE_74K): Update PROCESSOR_* names.
	* config/mips/mips.c (mips_cpu_info): Add 24kf2_1 as a synonym
	for 24kf.  Add 24kf1_1 and 24kfx as synonyms for 24kx.  Likewise
	the 24ke*, 34k* and 74k* processors.  Update PROCESSOR_* names.
	(mips_rtx_cost_data): Update processor names in comments.
	(mips_issue_rate): Update PROCESSOR_* names.
	* config/mips/mips.md (cpu): Rename 24kf to 24kf2_1, 24kx to
	24kf1_1, 74kf to 74kf2_1 and 74kx to 74kf1_1.
	* config/mips/24k.md: Rename FPU-related r24k_* insn reservations
	to r24kf2_1_*.  Rename r24kx_* insn reservations to r24kf1_1_*.
	Update cpu attribute names.
	(r24k_fpu_iss): Rename this reservation to...
	(r24kf2_1_fpu_iss): ...this and update all uses.
	(r24kx_fpu_iss): Rename this reservation to...
	(r24kf1_1_fpu_iss): ...this and update all uses.
	* config/mips/74k.md: Rename FPU-related r74kf_* insn reservations
	to r74kf2_1_*.  Rename r74kx_* insn reservations to r74kf1_1_*.
	Update cpu attribute names.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@126266 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 130 insertions, 130 deletions

diff --git a/gcc/config/mips/24k.md b/gcc/config/mips/24k.md
index 79b74ca8f8b..21e527d6cdc 100644
--- a/gcc/config/mips/24k.md
+++ b/gcc/config/mips/24k.md
@@ -2,8 +2,8 @@
 ;; Contributed by Chao-ying Fu (fu@mips.com), Nigel Stephens (nigel@mips.com)
 ;;   and David Ung (davidu@mips.com)
 ;;
-;; The 24K is a single-issue processor with a half-clocked fpu.
-;; The 24Kx is 24k with 1:1 clocked fpu.
+;; The 24kf2_1 is a single-issue processor with a half-clocked fpu.
+;; The 24kf1_1 is 24k with 1:1 clocked fpu.
 ;;
 ;; References:
 ;;   "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04."
@@ -42,7 +42,7 @@
 
 ;; 1. Loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
 (define_insn_reservation "r24k_int_load" 2
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (eq_attr "type" "load"))
   "r24k_iss+r24k_ixu_arith")
 
@@ -54,7 +54,7 @@
 ;; (movn/movz is not matched, we'll need to split condmov to
 ;;  differentiate between integer/float moves)
 (define_insn_reservation "r24k_int_arith" 1
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (eq_attr "type" "arith,const,nop,shift,slt"))
   "r24k_iss+r24k_ixu_arith")
 
@@ -62,13 +62,13 @@
 ;; 3. Links: bgezal, bgezall, bltzal, bltzall, jal, jalr, jalx
 ;; 3a. jr/jalr consumer
 (define_insn_reservation "r24k_int_jump" 1
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (eq_attr "type" "call,jump"))
   "r24k_iss+r24k_ixu_arith")
 
 ;; 3b. branch consumer
 (define_insn_reservation "r24k_int_branch" 1
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (eq_attr "type" "branch"))
   "r24k_iss+r24k_ixu_arith")
 
@@ -76,38 +76,38 @@
 ;; 4. MDU: fully pipelined multiplier
 ;; mult - delivers result to hi/lo in 1 cycle (pipelined)
 (define_insn_reservation "r24k_int_mult" 1
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (eq_attr "type" "imul"))
   "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
 
 ;; madd, msub - delivers result to hi/lo in 1 cycle (pipelined)
 (define_insn_reservation "r24k_int_madd" 1
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (eq_attr "type" "imadd"))
   "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
 
 ;; mul - delivers result to gpr in 5 cycles
 (define_insn_reservation "r24k_int_mul3" 5
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (eq_attr "type" "imul3"))
   "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5")
 
 ;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
 (define_insn_reservation "r24k_int_mfhilo" 5
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (eq_attr "type" "mfhilo"))
   "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
 
 ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
 (define_insn_reservation "r24k_int_mthilo" 1
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (eq_attr "type" "mthilo"))
   "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
 
 ;; div - default to 36 cycles for 32bit operands.  Faster for 24bit, 16bit and
 ;; 8bit, but is tricky to identify.
 (define_insn_reservation "r24k_int_div" 36
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (eq_attr "type" "idiv"))
   "r24k_iss+(r24k_mul3a+r24k_mul3b+r24k_mul3c)*36")
 
@@ -115,14 +115,14 @@
 ;; 5. Cop: cfc1, di, ei, mfc0, mtc0
 ;; (Disabled until we add proper cop0 support)
 ;;(define_insn_reservation "r24k_int_cop" 3
-;;  (and (eq_attr "cpu" "24k,24kx")
+;;  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
 ;;       (eq_attr "type" "cop0"))
 ;;  "r24k_iss+r24k_ixu_arith")
 
 
 ;; 6. Store
 (define_insn_reservation "r24k_int_store" 1
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (and (eq_attr "type" "store")
 	    (eq_attr "mode" "!unknown")))
   "r24k_iss+r24k_ixu_arith")
@@ -132,7 +132,7 @@
 ;;     against store_data_bypass_p, which would then fail because cprestore
 ;;     does not have a normal SET pattern.
 (define_insn_reservation "r24k_unknown_store" 1
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (and (eq_attr "type" "store")
 	    (eq_attr "mode" "unknown")))
   "r24k_iss+r24k_ixu_arith")
@@ -140,7 +140,7 @@
 
 ;; 7. Multiple instructions
 (define_insn_reservation "r24k_int_multi" 1
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (eq_attr "type" "multi"))
   "r24k_iss+r24k_ixu_arith+r24k_fpu_arith+(r24k_mul3a+r24k_mul3b+r24k_mul3c)")
 
@@ -149,14 +149,14 @@
 ;;    rtls. They do not really affect scheduling latency, (blockage affects
 ;;    scheduling via log links, but not used here).
 (define_insn_reservation "r24k_int_unknown" 0
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (eq_attr "type" "unknown"))
   "r24k_iss")
 
 
 ;; 9. Prefetch
 (define_insn_reservation "r24k_int_prefetch" 1
-  (and (eq_attr "cpu" "24kc,24kf,24kx")
+  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
        (eq_attr "type" "prefetch,prefetchx"))
   "r24k_iss+r24k_ixu_arith")
 
@@ -223,233 +223,233 @@
 ;; These timings are therefore twice the values in the 24K manual,
 ;; which are quoted in fpu clocks.
 ;;
-;; The 24kx is a 24k configured with 1:1 cpu and fpu, so use
+;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use
 ;; the unscaled timings
 
-(define_reservation "r24k_fpu_iss"	"r24k_iss+(r24k_fpu_arith*2)")
+(define_reservation "r24kf2_1_fpu_iss"	"r24k_iss+(r24k_fpu_arith*2)")
 
 ;; fadd, fabs, fneg
-(define_insn_reservation "r24k_fadd" 8
-  (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fadd" 8
+  (and (eq_attr "cpu" "24kf2_1")
        (eq_attr "type" "fadd,fabs,fneg"))
-  "r24k_fpu_iss")
+  "r24kf2_1_fpu_iss")
 
 ;; fmove, fcmove
-(define_insn_reservation "r24k_fmove" 8
-  (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fmove" 8
+  (and (eq_attr "cpu" "24kf2_1")
        (eq_attr "type" "fmove,condmove"))
-  "r24k_fpu_iss")
+  "r24kf2_1_fpu_iss")
 
 ;; fload
-(define_insn_reservation "r24k_fload" 6
-  (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fload" 6
+  (and (eq_attr "cpu" "24kf2_1")
        (eq_attr "type" "fpload,fpidxload"))
-  "r24k_fpu_iss")
+  "r24kf2_1_fpu_iss")
 
 ;; fstore
-(define_insn_reservation "r24k_fstore" 2
-  (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fstore" 2
+  (and (eq_attr "cpu" "24kf2_1")
        (eq_attr "type" "fpstore"))
-  "r24k_fpu_iss")
+  "r24kf2_1_fpu_iss")
 
 ;; fmul, fmadd
-(define_insn_reservation "r24k_fmul_sf" 8
-  (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fmul_sf" 8
+  (and (eq_attr "cpu" "24kf2_1")
        (and (eq_attr "type" "fmul,fmadd")
 	    (eq_attr "mode" "SF")))
-  "r24k_fpu_iss")
+  "r24kf2_1_fpu_iss")
 
-(define_insn_reservation "r24k_fmul_df" 10
-  (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fmul_df" 10
+  (and (eq_attr "cpu" "24kf2_1")
        (and (eq_attr "type" "fmul,fmadd")
 	    (eq_attr "mode" "DF")))
-  "r24k_fpu_iss,(r24k_fpu_arith*2)")
+  "r24kf2_1_fpu_iss,(r24k_fpu_arith*2)")
 
 
 ;; fdiv, fsqrt, frsqrt
-(define_insn_reservation "r24k_fdiv_sf" 34
-  (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fdiv_sf" 34
+  (and (eq_attr "cpu" "24kf2_1")
        (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
 	    (eq_attr "mode" "SF")))
-  "r24k_fpu_iss,(r24k_fpu_arith*26)")
+  "r24kf2_1_fpu_iss,(r24k_fpu_arith*26)")
 
-(define_insn_reservation "r24k_fdiv_df" 64
-  (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fdiv_df" 64
+  (and (eq_attr "cpu" "24kf2_1")
        (and (eq_attr "type" "fdiv,fsqrt")
 	    (eq_attr "mode" "DF")))
-  "r24k_fpu_iss,(r24k_fpu_arith*56)")
+  "r24kf2_1_fpu_iss,(r24k_fpu_arith*56)")
 
 ;; frsqrt
-(define_insn_reservation "r24k_frsqrt_df" 70
-  (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_frsqrt_df" 70
+  (and (eq_attr "cpu" "24kf2_1")
        (and (eq_attr "type" "frsqrt")
 	    (eq_attr "mode" "DF")))
-  "r24k_fpu_iss,(r24k_fpu_arith*60)")
+  "r24kf2_1_fpu_iss,(r24k_fpu_arith*60)")
 
 ;; fcmp
-(define_insn_reservation "r24k_fcmp" 4
-  (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fcmp" 4
+  (and (eq_attr "cpu" "24kf2_1")
        (eq_attr "type" "fcmp"))
-  "r24k_fpu_iss")
+  "r24kf2_1_fpu_iss")
 
 ;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
-(define_bypass 2 "r24k_fcmp" "r24k_fmove")
+(define_bypass 2 "r24kf2_1_fcmp" "r24kf2_1_fmove")
 
 ;; fcvt (cvt.d.s, cvt.[sd].[wl])
-(define_insn_reservation "r24k_fcvt_i2f_s2d" 8
-  (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fcvt_i2f_s2d" 8
+  (and (eq_attr "cpu" "24kf2_1")
        (and (eq_attr "type" "fcvt")
 	    (eq_attr "cnv_mode" "I2S,I2D,S2D")))
-  "r24k_fpu_iss")
+  "r24kf2_1_fpu_iss")
 
 ;; fcvt (cvt.s.d)
-(define_insn_reservation "r24k_fcvt_s2d" 12
-  (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fcvt_s2d" 12
+  (and (eq_attr "cpu" "24kf2_1")
        (and (eq_attr "type" "fcvt")
 	    (eq_attr "cnv_mode" "D2S")))
-  "r24k_fpu_iss")
+  "r24kf2_1_fpu_iss")
 
 ;; fcvt (cvt.[wl].[sd], etc)
-(define_insn_reservation "r24k_fcvt_f2i" 10
-  (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fcvt_f2i" 10
+  (and (eq_attr "cpu" "24kf2_1")
        (and (eq_attr "type" "fcvt")
 	    (eq_attr "cnv_mode" "S2I,D2I")))
-  "r24k_fpu_iss")
+  "r24kf2_1_fpu_iss")
 
 ;; fxfer (mfc1, mfhc1, mtc1, mthc1)
-(define_insn_reservation "r24k_fxfer" 4
-  (and (eq_attr "cpu" "24kf")
+(define_insn_reservation "r24kf2_1_fxfer" 4
+  (and (eq_attr "cpu" "24kf2_1")
        (eq_attr "type" "mfc,mtc"))
-  "r24k_fpu_iss")
+  "r24kf2_1_fpu_iss")
 
 ;; --------------------------------------------------------------
 ;; Bypass to Consumer
 ;; --------------------------------------------------------------
-;; r24k_fcvt_f2i->l/s base : 11 cycles
-;; r24k_fcvt_f2i->prefetch : 11 cycles
-(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_load")
-(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
-(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_prefetch")
-
-;; r24k_fxfer->l/s base : 5 cycles
-;; r24k_fxfer->prefetch : 5 cycles
-(define_bypass 5 "r24k_fxfer" "r24k_int_load")
-(define_bypass 5 "r24k_fxfer" "r24k_int_store" "!store_data_bypass_p")
-(define_bypass 5 "r24k_fxfer" "r24k_int_prefetch")
+;; r24kf2_1_fcvt_f2i->l/s base : 11 cycles
+;; r24kf2_1_fcvt_f2i->prefetch : 11 cycles
+(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_load")
+(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_prefetch")
+
+;; r24kf2_1_fxfer->l/s base : 5 cycles
+;; r24kf2_1_fxfer->prefetch : 5 cycles
+(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_load")
+(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_prefetch")
 
 ;; --------------------------------------------------------------
-;; The 24kx is a 24k configured with 1:1 cpu and fpu, so use
+;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use
 ;; the unscaled timings
 ;; --------------------------------------------------------------
 
-(define_reservation "r24kx_fpu_iss"	"r24k_iss+r24k_fpu_arith")
+(define_reservation "r24kf1_1_fpu_iss"	"r24k_iss+r24k_fpu_arith")
 
 ;; fadd, fabs, fneg
-(define_insn_reservation "r24kx_fadd" 4
-  (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fadd" 4
+  (and (eq_attr "cpu" "24kf1_1")
        (eq_attr "type" "fadd,fabs,fneg"))
-  "r24kx_fpu_iss")
+  "r24kf1_1_fpu_iss")
 
 ;; fmove, fcmove
-(define_insn_reservation "r24kx_fmove" 4
-  (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fmove" 4
+  (and (eq_attr "cpu" "24kf1_1")
        (eq_attr "type" "fmove,condmove"))
-  "r24kx_fpu_iss")
+  "r24kf1_1_fpu_iss")
 
 ;; fload
-(define_insn_reservation "r24kx_fload" 3
-  (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fload" 3
+  (and (eq_attr "cpu" "24kf1_1")
        (eq_attr "type" "fpload,fpidxload"))
-  "r24kx_fpu_iss")
+  "r24kf1_1_fpu_iss")
 
 ;; fstore
-(define_insn_reservation "r24kx_fstore" 1
-  (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fstore" 1
+  (and (eq_attr "cpu" "24kf1_1")
        (eq_attr "type" "fpstore"))
-  "r24kx_fpu_iss")
+  "r24kf1_1_fpu_iss")
 
 ;; fmul, fmadd
-(define_insn_reservation "r24kx_fmul_sf" 4
-  (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fmul_sf" 4
+  (and (eq_attr "cpu" "24kf1_1")
        (and (eq_attr "type" "fmul,fmadd")
 	    (eq_attr "mode" "SF")))
-  "r24kx_fpu_iss")
+  "r24kf1_1_fpu_iss")
 
-(define_insn_reservation "r24kx_fmul_df" 5
-  (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fmul_df" 5
+  (and (eq_attr "cpu" "24kf1_1")
        (and (eq_attr "type" "fmul,fmadd")
 	    (eq_attr "mode" "DF")))
-  "r24kx_fpu_iss,r24k_fpu_arith")
+  "r24kf1_1_fpu_iss,r24k_fpu_arith")
 
 
 ;; fdiv, fsqrt, frsqrt
-(define_insn_reservation "r24kx_fdiv_sf" 17
-  (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fdiv_sf" 17
+  (and (eq_attr "cpu" "24kf1_1")
        (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
 	    (eq_attr "mode" "SF")))
-  "r24kx_fpu_iss,(r24k_fpu_arith*13)")
+  "r24kf1_1_fpu_iss,(r24k_fpu_arith*13)")
 
-(define_insn_reservation "r24kx_fdiv_df" 32
-  (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fdiv_df" 32
+  (and (eq_attr "cpu" "24kf1_1")
        (and (eq_attr "type" "fdiv,fsqrt")
 	    (eq_attr "mode" "DF")))
-  "r24kx_fpu_iss,(r24k_fpu_arith*28)")
+  "r24kf1_1_fpu_iss,(r24k_fpu_arith*28)")
 
 ;; frsqrt
-(define_insn_reservation "r24kx_frsqrt_df" 35
-  (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_frsqrt_df" 35
+  (and (eq_attr "cpu" "24kf1_1")
        (and (eq_attr "type" "frsqrt")
 	    (eq_attr "mode" "DF")))
-  "r24kx_fpu_iss,(r24k_fpu_arith*30)")
+  "r24kf1_1_fpu_iss,(r24k_fpu_arith*30)")
 
 ;; fcmp
-(define_insn_reservation "r24kx_fcmp" 2
-  (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fcmp" 2
+  (and (eq_attr "cpu" "24kf1_1")
        (eq_attr "type" "fcmp"))
-  "r24kx_fpu_iss")
+  "r24kf1_1_fpu_iss")
 
 ;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
-(define_bypass 1 "r24kx_fcmp" "r24kx_fmove")
+(define_bypass 1 "r24kf1_1_fcmp" "r24kf1_1_fmove")
 
 ;; fcvt (cvt.d.s, cvt.[sd].[wl])
-(define_insn_reservation "r24kx_fcvt_i2f_s2d" 4
-  (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fcvt_i2f_s2d" 4
+  (and (eq_attr "cpu" "24kf1_1")
        (and (eq_attr "type" "fcvt")
 	    (eq_attr "cnv_mode" "I2S,I2D,S2D")))
-  "r24kx_fpu_iss")
+  "r24kf1_1_fpu_iss")
 
 ;; fcvt (cvt.s.d)
-(define_insn_reservation "r24kx_fcvt_s2d" 6
-  (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fcvt_s2d" 6
+  (and (eq_attr "cpu" "24kf1_1")
        (and (eq_attr "type" "fcvt")
 	    (eq_attr "cnv_mode" "D2S")))
-  "r24kx_fpu_iss")
+  "r24kf1_1_fpu_iss")
 
 ;; fcvt (cvt.[wl].[sd], etc)
-(define_insn_reservation "r24kx_fcvt_f2i" 5
-  (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fcvt_f2i" 5
+  (and (eq_attr "cpu" "24kf1_1")
        (and (eq_attr "type" "fcvt")
 	    (eq_attr "cnv_mode" "S2I,D2I")))
-  "r24kx_fpu_iss")
+  "r24kf1_1_fpu_iss")
 
 ;; fxfer (mfc1, mfhc1, mtc1, mthc1)
-(define_insn_reservation "r24kx_fxfer" 2
-  (and (eq_attr "cpu" "24kx")
+(define_insn_reservation "r24kf1_1_fxfer" 2
+  (and (eq_attr "cpu" "24kf1_1")
        (eq_attr "type" "mfc,mtc"))
-  "r24kx_fpu_iss")
+  "r24kf1_1_fpu_iss")
 
 ;; --------------------------------------------------------------
 ;; Bypass to Consumer
 ;; --------------------------------------------------------------
-;; r24kx_fcvt_f2i->l/s base : 6 cycles
-;; r24kx_fcvt_f2i->prefetch : 6 cycles
-(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_load")
-(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
-(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_prefetch")
-
-;; r24kx_fxfer->l/s base : 3 cycles
-;; r24kx_fxfer->prefetch : 3 cycles
-(define_bypass 3 "r24kx_fxfer" "r24k_int_load")
-(define_bypass 3 "r24kx_fxfer" "r24k_int_store" "!store_data_bypass_p")
-(define_bypass 3 "r24kx_fxfer" "r24k_int_prefetch")
+;; r24kf1_1_fcvt_f2i->l/s base : 6 cycles
+;; r24kf1_1_fcvt_f2i->prefetch : 6 cycles
+(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_load")
+(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_prefetch")
+
+;; r24kf1_1_fxfer->l/s base : 3 cycles
+;; r24kf1_1_fxfer->prefetch : 3 cycles
+(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_load")
+(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_prefetch")