* config/m32c/m32c.c (m32c_emit_epilogue): Don't try to push

registers if we already know there aren't any.
(m32c_emit_epilogue): Don't emit a barrier here.
(m32c_emit_eh_epilogue): Likewise.
* config/m32c/blkmov.md (movstr): Don't fail on wrong-type
operands at expand time.
* config/m32c/m32c.h (WCHAR_TYPE_SIZE): Change to 4 to match "long
int" wchar type.
(REG_CLASS_CONTENTS, reg_class, REG_CLASS_NAMES): Remove
duplicates.  Provide aliases instead.
* config/m32c/prologue.md (eh_return): Emit a barrier here.
(eh_epilogue): Add a "(return)" here as a hint to other parts of
the compiler.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@172735 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 8 insertions, 15 deletions

diff --git a/gcc/config/m32c/m32c.h b/gcc/config/m32c/m32c.h
index 7b5a5484582..6016ee56a13 100644
--- a/gcc/config/m32c/m32c.h
+++ b/gcc/config/m32c/m32c.h
@@ -201,7 +201,7 @@ machine_function;
 #define WCHAR_TYPE "long int"
 
 #undef  WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
+#define WCHAR_TYPE_SIZE 32
 
 /* REGISTER USAGE */
 
@@ -288,19 +288,15 @@ machine_function;
   { 0x00000003 }, /* R02 - r0r2 */\
   { 0x0000000c }, /* R13 - r1r3 */\
   { 0x00000005 }, /* HL  - r0 r1 */\
-  { 0x00000005 }, /* QI  - r0 r1 */\
   { 0x0000000a }, /* R23 - r2 r3 */\
   { 0x0000000f }, /* R03 - r0r2 r1r3 */\
-  { 0x0000000f }, /* DI  - r0r2r1r3 + mems */\
   { 0x00000010 }, /* A0  - a0 */\
   { 0x00000020 }, /* A1  - a1 */\
   { 0x00000030 }, /* A   - a0 a1 */\
   { 0x000000f0 }, /* AD  - a0 a1 sb fp */\
   { 0x000001f0 }, /* PS  - a0 a1 sb fp sp */\
-  { 0x0000000f }, /* SI  - r0r2 r1r3 a0a1 */\
-  { 0x0000003f }, /* HI  - r0 r1 r2 r3 a0 a1 */\
   { 0x00000033 }, /* R02A  - r0r2 a0 a1 */ \
-  { 0x0000003f }, /* RA  - r0..r3 a0 a1 */\
+  { 0x0000003f }, /* RA  - r0 r1 r2 r3 a0 a1 */\
   { 0x0000007f }, /* GENERAL */\
   { 0x00000400 }, /* FLG */\
   { 0x000001ff }, /* HC  - r0l r1 r2 r3 a0 a1 sb fb sp */\
@@ -311,9 +307,14 @@ machine_function;
   { 0x000ff00f }, /* R03_MEM */\
   { 0x000ff03f }, /* A_HI_MEM */\
   { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
-  { 0x000ff1ff }, /* ALL */\
+  { 0x000ff5ff }, /* ALL */\
 }
 
+#define QI_REGS HL_REGS
+#define HI_REGS RA_REGS
+#define SI_REGS R03_REGS
+#define DI_REGS R03_REGS
+
 enum reg_class
 {
   NO_REGS,
@@ -328,17 +329,13 @@ enum reg_class
   R02_REGS,
   R13_REGS,
   HL_REGS,
-  QI_REGS,
   R23_REGS,
   R03_REGS,
-  DI_REGS,
   A0_REGS,
   A1_REGS,
   A_REGS,
   AD_REGS,
   PS_REGS,
-  SI_REGS,
-  HI_REGS,
   R02A_REGS,
   RA_REGS,
   GENERAL_REGS,
@@ -370,17 +367,13 @@ enum reg_class
 "R02_REGS", \
 "R13_REGS", \
 "HL_REGS", \
-"QI_REGS", \
 "R23_REGS", \
 "R03_REGS", \
-"DI_REGS", \
 "A0_REGS", \
 "A1_REGS", \
 "A_REGS", \
 "AD_REGS", \
 "PS_REGS", \
-"SI_REGS", \
-"HI_REGS", \
 "R02A_REGS", \
 "RA_REGS", \
 "GENERAL_REGS", \