2006-06-26 DJ Delorie <dj@redhat.com>

	* config/m32c/m32c.c (m32c_print_operand): Fix sign-merging logic.

2006-06-26  Naveen H.S  <naveenh@kpitcummins.com>
	    Jayant Sonar  <jayants@kpitcummins.com>
	    Jaydeep Vipradas  <jaydeepv@kpitcummins.com>

	* config/m32c/addsub.md (addsi3, addsi3_1, addsi3_2): New.
	(subsi3, subsi3_1, subsi3_2): New.
	* config/m32c/bitops.md (andsi3, iorsi3, xorsi3): New.
	* config/m32c/mov.md (SI mov peephole): New.
	* config/m32c/m32.c (m32c_immd_dbl_mov): New.
	* config/m32c/m32c-protos.h (m32c_immd_dbl_mov): New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@115023 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 95 insertions, 0 deletions

diff --git a/gcc/config/m32c/addsub.md b/gcc/config/m32c/addsub.md
index 83587564ebd..45bd3cd3664 100644
--- a/gcc/config/m32c/addsub.md
+++ b/gcc/config/m32c/addsub.md
@@ -72,6 +72,56 @@
   [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,n,n")]
   )
 
+(define_expand "addsi3"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
+        (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0")
+                 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
+  "TARGET_A24 ||TARGET_A16"
+  ""
+  )
+
+(define_insn "addsi3_1"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm,RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
+        (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
+                 (match_operand 2 "mrai_operand" "IU2,IU2,i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
+  "TARGET_A16"
+  "*
+  
+  switch (which_alternative)
+    { 
+    case 0:
+      return \"add.w %X2,%h0\;adcf.w %H0\";
+    case 1:
+      return \"add.w %X2,%h0\;adcf.w %H0\";
+    case 2:
+      output_asm_insn (\"add.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"adc.w %X2,%H0\";
+    case 3:
+      return \"add.w %h2,%h0\;adc.w %H2,%H0\";
+    case 4:
+      output_asm_insn (\"add.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"adc.w %X2,%H0\";
+    case 5:
+      return \"add.w %h2,%h0\;adc.w %H2,%H0\";
+    case 6:
+      return \"add.w %h2,%h0\;adc.w %H2,%H0\";
+    case 7:
+      return \"add.w %h2,%h0\;adc.w %H2,%H0\";
+    }"
+  [(set_attr "flags" "x,x,x,x,x,x,x,x")]
+)
+
+(define_insn "addsi3_2"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
+        (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0")
+                 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
+  "TARGET_A24"
+  "add.l\t%2,%0"
+  [(set_attr "flags" "oszc")]
+)
+
 (define_insn "subqi3"
   [(set (match_operand:QI 0 "mra_or_sp_operand"
 		   "=SdRhl,SdRhl,??Rmm,??Rmm, Raa,Raa,SdRhl,??Rmm, *Rsp")
@@ -111,6 +161,51 @@
   [(set_attr "flags" "oszc")]
   )
 
+(define_expand "subsi3"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
+        (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0")
+                  (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
+  "TARGET_A24 ||TARGET_A16"
+  ""
+)
+
+(define_insn "subsi3_1"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
+        (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0,0,0")
+                  (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
+  "TARGET_A16"
+  "*
+  switch (which_alternative)
+    {
+    case 0:
+      output_asm_insn (\"sub.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"sbb.w %X2,%H0\";
+    case 1:
+      return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
+    case 2:
+      output_asm_insn (\"sub.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"sbb.w %X2,%H0\";
+    case 3:
+      return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
+    case 4:
+      return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
+    case 5:
+      return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
+    }"
+  [(set_attr "flags" "x,x,x,x,x,x")]
+)
+
+(define_insn "subsi3_2"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
+        (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0")
+                  (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
+  "TARGET_A24"
+  "sub.l\t%2,%0"
+  [(set_attr "flags" "oszc,oszc,oszc,oszc")]
+)
+
 (define_insn "negqi2"
   [(set (match_operand:QI 0 "mra_operand" "=SdRhl,??Rmm")
 	(neg:QI (match_operand:QI 1 "mra_operand" "0,0")))]