re PR target/36079 (cld instruction is not emitted anymore.)

	PR target/36079
	* configure.ac: Handle --enable-cld.
	* configure: Regenerated.
	* config.gcc: Add USE_IX86_CLD to tm_defines for x86 targets.
	* config/i386/i386.h (struct machine_function): Add needs_cld field.
	(ix86_current_function_needs_cld): New define.
	* config/i386/i386.md (UNSPEC_CLD): New unspec volatile constant.
	(cld): New isns pattern.
	(strmov_singleop, rep_mov, strset_singleop, rep_stos, cmpstrnqi_nz_1,
	cmpstrnqi_1, strlenqi_1): Set ix86_current_function_needs_cld flag.
	* config/i386/i386.opt (mcld): New option.
	* config/i386/i386.c (ix86_expand_prologue): Emit cld insn if
	TARGET_CLD and ix86_current_function_needs_cld.
	(override_options): Use -mcld by default for 32-bit code if
	USE_IX86_CLD.

	* doc/install.texi (Options specification): Document --enable-cld.
	* doc/invoke.texi (Machine Dependent Options)
        [i386 and x86-64 Options]: Add -mcld option.
        (Intel 386 and AMD x86-64 Options): Document -mcld option.

From-SVN: r135792

4 files changed, 34 insertions, 9 deletions

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 31a691ff38b..0f140c8adf7 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2764,6 +2764,12 @@ override_options (void)
      can be optimized to ap = __builtin_next_arg (0).  */
   if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
     targetm.expand_builtin_va_start = NULL;
+
+#ifdef USE_IX86_CLD
+  /* Use -mcld by default for 32-bit code if configured with --enable-cld.  */
+  if (!TARGET_64BIT)
+    target_flags |= MASK_CLD & ~target_flags_explicit;
+#endif
 }
 
 /* Return true if this goes in large data/bss.  */
@@ -6597,6 +6603,10 @@ ix86_expand_prologue (void)
 	emit_insn (gen_prologue_use (pic_offset_table_rtx));
       emit_insn (gen_blockage ());
     }
+
+  /* Emit cld instruction if stringops are used in the function.  */
+  if (TARGET_CLD && ix86_current_function_needs_cld)
+    emit_insn (gen_cld ());
 }
 
 /* Emit code to restore saved registers using MOV insns.  First register
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 72ead0795c2..0b5ca139350 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2432,8 +2432,9 @@ struct machine_function GTY(())
   int save_varrargs_registers;
   int accesses_prev_frame;
   int optimize_mode_switching[MAX_386_ENTITIES];
-  /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
-     determine the style used.  */
+  int needs_cld;
+  /* Set by ix86_compute_frame_layout and used by prologue/epilogue
+     expander to determine the style used.  */
   int use_fast_prologue_epilogue;
   /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
      for.  */
@@ -2453,6 +2454,7 @@ struct machine_function GTY(())
 #define ix86_stack_locals (cfun->machine->stack_locals)
 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
+#define ix86_current_function_needs_cld (cfun->machine->needs_cld)
 #define ix86_tls_descriptor_calls_expanded_in_cfun \
   (cfun->machine->tls_descriptor_call_expanded_p)
 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index a021e7c75e7..8f91de08519 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -213,6 +213,7 @@
    (UNSPECV_XCHG		12)
    (UNSPECV_LOCK		13)
    (UNSPECV_PROLOGUE_USE	14)
+   (UNSPECV_CLD			15)
   ])
 
 ;; Constants to represent pcomtrue/pcomfalse variants
@@ -18374,6 +18375,14 @@
 
 ;; Block operation instructions
 
+(define_insn "cld"
+  [(unspec_volatile [(const_int 0)] UNSPECV_CLD)]
+  ""
+  "cld"
+  [(set_attr "length" "1")
+   (set_attr "length_immediate" "0")
+   (set_attr "modrm" "0")])
+
 (define_expand "movmemsi"
   [(use (match_operand:BLK 0 "memory_operand" ""))
    (use (match_operand:BLK 1 "memory_operand" ""))
@@ -18446,7 +18455,7 @@
 	      (set (match_operand 2 "register_operand" "")
 		   (match_operand 5 "" ""))])]
   "TARGET_SINGLE_STRINGOP || optimize_size"
-  "")
+  "ix86_current_function_needs_cld = 1;")
 
 (define_insn "*strmovdi_rex_1"
   [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
@@ -18563,7 +18572,7 @@
 		   (match_operand 3 "memory_operand" ""))
 	      (use (match_dup 4))])]
   ""
-  "")
+  "ix86_current_function_needs_cld = 1;")
 
 (define_insn "*rep_movdi_rex64"
   [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
@@ -18723,7 +18732,7 @@
 	      (set (match_operand 0 "register_operand" "")
 		   (match_operand 3 "" ""))])]
   "TARGET_SINGLE_STRINGOP || optimize_size"
-  "")
+  "ix86_current_function_needs_cld = 1;")
 
 (define_insn "*strsetdi_rex_1"
   [(set (mem:DI (match_operand:DI 1 "register_operand" "0"))
@@ -18817,7 +18826,7 @@
 	      (use (match_operand 3 "register_operand" ""))
 	      (use (match_dup 1))])]
   ""
-  "")
+  "ix86_current_function_needs_cld = 1;")
 
 (define_insn "*rep_stosdi_rex64"
   [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
@@ -18993,7 +19002,7 @@
 	      (clobber (match_operand 1 "register_operand" ""))
 	      (clobber (match_dup 2))])]
   ""
-  "")
+  "ix86_current_function_needs_cld = 1;")
 
 (define_insn "*cmpstrnqi_nz_1"
   [(set (reg:CC FLAGS_REG)
@@ -19040,7 +19049,7 @@
 	      (clobber (match_operand 1 "register_operand" ""))
 	      (clobber (match_dup 2))])]
   ""
-  "")
+  "ix86_current_function_needs_cld = 1;")
 
 (define_insn "*cmpstrnqi_1"
   [(set (reg:CC FLAGS_REG)
@@ -19109,7 +19118,7 @@
 	      (clobber (match_operand 1 "register_operand" ""))
 	      (clobber (reg:CC FLAGS_REG))])]
   ""
-  "")
+  "ix86_current_function_needs_cld = 1;")
 
 (define_insn "*strlenqi_1"
   [(set (match_operand:SI 0 "register_operand" "=&c")
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 45af24acac4..75c94ba771e 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -250,6 +250,10 @@ Support SSE5 built-in functions and code generation
 
 ;; Instruction support
 
+mcld
+Target Report Mask(CLD)
+Generate cld instruction in the function prologue.
+
 mabm
 Target Report RejectNegative Var(x86_abm)
 Support code generation of Advanced Bit Manipulation (ABM) instructions.