diff options
| author | jakub <jakub@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-07-25 13:35:17 +0000 |
|---|---|---|
| committer | jakub <jakub@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-07-25 13:35:17 +0000 |
| commit | ed4be3d211159458682d14ab3af3f0e69f323f30 (patch) | |
| tree | df9284c91a2cdb772aea9ba75ef021025723d3b2 /gcc/config/i386 | |
| parent | cefc7aa375341a4ade53b2a94c6c2063081a1da5 (diff) | |
| download | gcc-ed4be3d211159458682d14ab3af3f0e69f323f30.tar.gz | |
PR target/81532
* config/i386/constraints.md (Yd, Ye): Use ALL_SSE_REGS for
TARGET_AVX512DQ rather than TARGET_AVX512BW.
* gcc.target/i386/pr80833-3.c: New test.
* gcc.target/i386/avx512dq-pr81532.c: New test.
* gcc.target/i386/avx512bw-pr81532.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@250520 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/i386')
| -rw-r--r-- | gcc/config/i386/constraints.md | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index f94e274358b..98c05c9ebab 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -138,19 +138,19 @@ (define_register_constraint "Yd" "TARGET_INTER_UNIT_MOVES_TO_VEC - ? (TARGET_AVX512BW + ? (TARGET_AVX512DQ ? ALL_SSE_REGS : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) : NO_REGS" - "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.") + "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.") (define_register_constraint "Ye" "TARGET_INTER_UNIT_MOVES_FROM_VEC - ? (TARGET_AVX512BW + ? (TARGET_AVX512DQ ? ALL_SSE_REGS : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) : NO_REGS" - "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.") + "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.") (define_register_constraint "Ym" "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS" |