diff options
| author | echristo <echristo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2007-06-14 21:43:45 +0000 |
|---|---|---|
| committer | echristo <echristo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2007-06-14 21:43:45 +0000 |
| commit | 0bb48c335ac793188d8a82ad775f9e3f9aa6cae5 (patch) | |
| tree | afd7d0e47d1ee723820c01ca4eae2c6b7a226b27 /gcc/config/i386 | |
| parent | f918309c297523569843ca4a4acc2841e7bc2c42 (diff) | |
| download | gcc-0bb48c335ac793188d8a82ad775f9e3f9aa6cae5.tar.gz | |
2007-06-14 Eric Christopher <echristo@apple.com>
* config/i386/sse.md (movdi_to_sse): Rewrite body.
(movv4sf): Use gcc_unreachable instead of abort.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@125723 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/i386')
| -rw-r--r-- | gcc/config/i386/sse.md | 20 |
1 files changed, 7 insertions, 13 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 2a4606fffe0..c74c0f7fe69 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -108,9 +108,8 @@ "&& reload_completed" [(const_int 0)] { - switch (which_alternative) - { - case 0: + if (register_operand (operands[1], DImode)) + { /* The DImode arrived in a pair of integral registers (e.g. %edx:%eax). Assemble the 64-bit DImode value in an xmm register. */ emit_insn (gen_sse2_loadld (operands[0], CONST0_RTX (V4SImode), @@ -118,16 +117,11 @@ emit_insn (gen_sse2_loadld (operands[2], CONST0_RTX (V4SImode), gen_rtx_SUBREG (SImode, operands[1], 4))); emit_insn (gen_sse2_punpckldq (operands[0], operands[0], operands[2])); - break; - - case 1: - emit_insn (gen_vec_concatv2di (operands[0], operands[1], const0_rtx)); - break; - - default: - gcc_unreachable (); } - DONE; + else if (memory_operand (operands[1], DImode)) + emit_insn (gen_vec_concatv2di (gen_lowpart (V2DImode, operands[0]), operands[1], const0_rtx)); + else + gcc_unreachable (); }) (define_expand "movv4sf" @@ -154,7 +148,7 @@ case 2: return "movaps\t{%1, %0|%0, %1}"; default: - abort(); + gcc_unreachable (); } } [(set_attr "type" "sselog1,ssemov,ssemov") |