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| author | hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-11-12 13:52:08 +0000 |
|---|---|---|
| committer | hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-11-12 13:52:08 +0000 |
| commit | 6d3c030fe155dda153688b331c17ba52017f758f (patch) | |
| tree | b0df24bfc1dfe284eac97a5b72db64fd1d9a428f /gcc/config/i386/x86-tune.def | |
| parent | 5cbbe3dec78c64b6ad7b89357384e0bced781257 (diff) | |
| download | gcc-6d3c030fe155dda153688b331c17ba52017f758f.tar.gz | |
Turn on SEE unaligned load and store for Haswell
PR target/59088
* config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL):
Set for m_HASWELL.
(X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Set for m_HASWELL.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@204701 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/i386/x86-tune.def')
| -rw-r--r-- | gcc/config/i386/x86-tune.def | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 54867d2f31f..4c13c3a0ec6 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -318,12 +318,12 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill", /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL: Use movups for misaligned loads instead of a sequence loading registers by parts. */ DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal", - m_COREI7 | m_COREI7_AVX | m_AMDFAM10 | m_BDVER | m_BTVER | m_SLM | m_GENERIC) + m_COREI7 | m_COREI7_AVX | m_HASWELL | m_AMDFAM10 | m_BDVER | m_BTVER | m_SLM | m_GENERIC) /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead of a sequence loading registers by parts. */ DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal", - m_COREI7 | m_COREI7_AVX | m_BDVER | m_SLM | m_GENERIC) + m_COREI7 | m_COREI7_AVX | m_HASWELL | m_BDVER | m_SLM | m_GENERIC) /* Use packed single precision instructions where posisble. I.e. movups instead of movupd. */ |