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author | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-11-26 10:55:09 +0000 |
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committer | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-11-26 10:55:09 +0000 |
commit | 2dbf9f4d4d7639d91466c3be3fb31a517d1d693f (patch) | |
tree | 68e5f5d51955cac4e90eacfe13c5d0b2739a5d48 /gcc/config/i386/sync.md | |
parent | 9ddeff7e93a8cf42ff1904e4a95db0a98d6761f3 (diff) | |
download | gcc-2dbf9f4d4d7639d91466c3be3fb31a517d1d693f.tar.gz |
* config/i386/sync.md (movdi_via_fpu): Add %Z insn suffixes.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@181739 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/i386/sync.md')
-rw-r--r-- | gcc/config/i386/sync.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index 542d3b87882..5799b0aca50 100644 --- a/gcc/config/i386/sync.md +++ b/gcc/config/i386/sync.md @@ -123,7 +123,7 @@ DONE; }) -;; ??? From volume 3 section 7.1.1 Guaranteed Atomic Operations, +;; ??? From volume 3 section 8.1.1 Guaranteed Atomic Operations, ;; Only beginning at Pentium family processors do we get any guarantee of ;; atomicity in aligned 64-bit quantities. Beginning at P6, we get a ;; guarantee for 64-bit accesses that do not cross a cacheline boundary. @@ -281,7 +281,7 @@ (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_MOVA)) (clobber (match_operand:DF 2 "register_operand" "=f"))] "TARGET_80387" - "fild\t%1\;fistp\t%0" + "fild%Z1\t%1\;fistp%Z0\t%0" [(set_attr "type" "multi") ;; Worst case based on full sib+offset32 addressing modes (set_attr "length" "14")]) |