ChangeLog entry:

        * coretypes (MEMMODEL_MASK): New.
        * builtins.c (get_memmodel): Add val. Call target.memmodel_check
        and return new variable.
        (expand_builtin_atomic_exchange):  Mask memmodel values.
        (expand_builtin_atomic_compare_exchange): Ditto.
        (expand_builtin_atomic_load): Ditto.
        (expand_builtin_atomic_store): Ditto.
        (expand_builtin_atomic_clear): Ditto.
        * doc/extend.texi: Mention port-dependent memory model flags.
        * config/i386/cpuid.h (bit_HLE): New.
        * config/i386/driver-i386.c (host_detect_local_cpu): Detect
        HLE support.
        * config/i386/i386-protos.h (ix86_generate_hle_prefix): New.
        * config/i386/i386-c.c (ix86_target_macros_internal): Set
        HLE defines.
        (ix86_target_string)<-mhle>: New.
        (ix86_valid_target_attribute_inner_p)<OPT_mhle>: Ditto.
        * config/i386/i386.c (ix86_target_string)<OPTION_MASK_ISA_HLE>:
        New.
        (ix86_valid_target_attribute_inner_p)<OPT_mhle>: Ditto.
        (ix86_option_override_internal)<PTA_HLE>: New switch, set it
        enabled for generic, generic64 and core-avx2.
        (ix86_print_operand): Generate HLE lock prefixes.
        (ix86_memmodel_check): New.
        (TARGET_MEMMODEL_CHECK): Ditto.
        * config/i386/i386.h (OPTION_ISA_HLE): Ditto.
        (IX86_HLE_ACQUIRE): Ditto.
        (IX86_HLE_RELEASE): Ditto.
        * config/i386/i386.h (ix86_generate_hle_prefix): Ditto.
        * config/i386/i386.opt (mhle): Ditto.
        * config/i386/sync.md(atomic_compare_and_swap<mode>): Pass
        success model to instruction emitter.
        (atomic_fetch_add<mode>): Ditto.
        (atomic_exchange<mode>): Ditto.
        (atomic_add<mode>): Ditto.
        (atomic_sub<mode>): Ditto.
        (atomic_<code><mode>): Ditto.
        (*atomic_compare_and_swap_doubledi_pic): Ditto.
        (atomic_compare_and_swap_single<mode>): Define and use argument
        for success model.
        (atomic_compare_and_swap_double<mode>): Ditto.
        * configure.ac: Check if assembler support HLE prefixes.
        * configure: Regenerate.
        * config.in: Ditto.

testsuite/ChangeLog entry:

        * gcc.target/i386/hle-cmpxchg-acq-1.c: New.
        * gcc.target/i386/hle-cmpxchg-rel-1.c: Ditto.
        * gcc.target/i386/hle-add-acq-1.c: Ditto.
        * gcc.target/i386/hle-add-rel-1.c: Ditto.
        * gcc.target/i386/hle-and-acq-1.c: Ditto.
        * gcc.target/i386/hle-and-rel-1.c: Ditto.
        * gcc.target/i386/hle-or-acq-1.c: Ditto.
        * gcc.target/i386/hle-or-rel-1.c: Ditto.
        * gcc.target/i386/hle-sub-acq-1.c: Ditto.
        * gcc.target/i386/hle-sub-rel-1.c: Ditto.
        * gcc.target/i386/hle-xadd-acq-1.c: Ditto.
        * gcc.target/i386/hle-xadd-rel-1.c: Ditto.
        * gcc.target/i386/hle-xchg-acq-1.c: Ditto.
        * gcc.target/i386/hle-xchg-rel-1.c: Ditto.
        * gcc.target/i386/hle-xor-acq-1.c: Ditto.
        * gcc.target/i386/hle-xor-rel-1.c: Ditto.




git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@187051 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 27 insertions, 22 deletions

diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md
index faf65ba8a23..e02a949631e 100644
--- a/gcc/config/i386/sync.md
+++ b/gcc/config/i386/sync.md
@@ -315,8 +315,9 @@
    (match_operand:SI 7 "const_int_operand")]	;; failure model
   "TARGET_CMPXCHG"
 {
-  emit_insn (gen_atomic_compare_and_swap_single<mode>
-	     (operands[1], operands[2], operands[3], operands[4]));
+  emit_insn
+   (gen_atomic_compare_and_swap_single<mode>
+    (operands[1], operands[2], operands[3], operands[4], operands[6]));
   ix86_expand_setcc (operands[0], EQ, gen_rtx_REG (CCZmode, FLAGS_REG),
 		     const0_rtx);
   DONE;
@@ -344,8 +345,9 @@
 {
   if (<MODE>mode == DImode && TARGET_64BIT)
     {
-      emit_insn (gen_atomic_compare_and_swap_singledi
-		 (operands[1], operands[2], operands[3], operands[4]));
+      emit_insn
+       (gen_atomic_compare_and_swap_singledi
+	(operands[1], operands[2], operands[3], operands[4], operands[6]));
     }
   else
     {
@@ -370,7 +372,7 @@
 	mem = replace_equiv_address (mem, force_reg (Pmode, XEXP (mem, 0)));
 
       emit_insn (gen_atomic_compare_and_swap_double<mode>
-		 (lo_o, hi_o, mem, lo_e, hi_e, lo_n, hi_n));
+		 (lo_o, hi_o, mem, lo_e, hi_e, lo_n, hi_n, operands[6]));
     }
   ix86_expand_setcc (operands[0], EQ, gen_rtx_REG (CCZmode, FLAGS_REG),
 		     const0_rtx);
@@ -382,14 +384,15 @@
 	(unspec_volatile:SWI
 	  [(match_operand:SWI 1 "memory_operand" "+m")
 	   (match_operand:SWI 2 "register_operand" "0")
-	   (match_operand:SWI 3 "register_operand" "<r>")]
+	   (match_operand:SWI 3 "register_operand" "<r>")
+	   (match_operand:SI 4 "const_int_operand")]
 	  UNSPECV_CMPXCHG_1))
    (set (match_dup 1)
 	(unspec_volatile:SWI [(const_int 0)] UNSPECV_CMPXCHG_2))
    (set (reg:CCZ FLAGS_REG)
         (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG_3))]
   "TARGET_CMPXCHG"
-  "lock{%;} cmpxchg{<imodesuffix>}\t{%3, %1|%1, %3}")
+  "lock{%;} %K4cmpxchg{<imodesuffix>}\t{%3, %1|%1, %3}")
 
 ;; For double-word compare and swap, we are obliged to play tricks with
 ;; the input newval (op5:op6) because the Intel register numbering does
@@ -403,7 +406,8 @@
 	   (match_operand:<DCASHMODE> 3 "register_operand" "0")
 	   (match_operand:<DCASHMODE> 4 "register_operand" "1")
 	   (match_operand:<DCASHMODE> 5 "register_operand" "b")
-	   (match_operand:<DCASHMODE> 6 "register_operand" "c")]
+	   (match_operand:<DCASHMODE> 6 "register_operand" "c")
+	   (match_operand:SI 7 "const_int_operand")]
 	  UNSPECV_CMPXCHG_1))
    (set (match_operand:<DCASHMODE> 1 "register_operand" "=d")
 	(unspec_volatile:<DCASHMODE> [(const_int 0)] UNSPECV_CMPXCHG_2))
@@ -412,7 +416,7 @@
    (set (reg:CCZ FLAGS_REG)
         (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG_4))]
   ""
-  "lock{%;} cmpxchg<doublemodesuffix>b\t%2")
+  "lock{%;} %K7cmpxchg<doublemodesuffix>b\t%2")
 
 ;; Theoretically we'd like to use constraint "r" (any reg) for op5,
 ;; but that includes ecx.  If op5 and op6 are the same (like when
@@ -430,7 +434,8 @@
 	   (match_operand:SI 3 "register_operand" "0")
 	   (match_operand:SI 4 "register_operand" "1")
 	   (match_operand:SI 5 "register_operand" "SD")
-	   (match_operand:SI 6 "register_operand" "c")]
+	   (match_operand:SI 6 "register_operand" "c")
+	   (match_operand:SI 7 "const_int_operand")]
 	  UNSPECV_CMPXCHG_1))
    (set (match_operand:SI 1 "register_operand" "=d")
 	(unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_2))
@@ -439,7 +444,7 @@
    (set (reg:CCZ FLAGS_REG)
         (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG_4))]
   "!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
-  "xchg{l}\t%%ebx, %5\;lock{%;} cmpxchg8b\t%2\;xchg{l}\t%%ebx, %5")
+  "xchg{l}\t%%ebx, %5\;lock{%;} %K7cmpxchg8b\t%2\;xchg{l}\t%%ebx, %5")
 
 ;; For operand 2 nonmemory_operand predicate is used instead of
 ;; register_operand to allow combiner to better optimize atomic
@@ -455,7 +460,7 @@
 		  (match_operand:SWI 2 "nonmemory_operand" "0")))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_XADD"
-  "lock{%;} xadd{<imodesuffix>}\t{%0, %1|%1, %0}")
+  "lock{%;} %K3xadd{<imodesuffix>}\t{%0, %1|%1, %0}")
 
 ;; This peephole2 and following insn optimize
 ;; __sync_fetch_and_add (x, -N) == N into just lock {add,sub,inc,dec}
@@ -526,7 +531,7 @@
    (set (match_dup 1)
 	(match_operand:SWI 2 "register_operand" "0"))]		;; input
   ""
-  "xchg{<imodesuffix>}\t{%1, %0|%0, %1}")
+  "%K3xchg{<imodesuffix>}\t{%1, %0|%0, %1}")
 
 (define_insn "atomic_add<mode>"
   [(set (match_operand:SWI 0 "memory_operand" "+m")
@@ -541,15 +546,15 @@
   if (TARGET_USE_INCDEC)
     {
       if (operands[1] == const1_rtx)
-	return "lock{%;} inc{<imodesuffix>}\t%0";
+	return "lock{%;} %K2inc{<imodesuffix>}\t%0";
       if (operands[1] == constm1_rtx)
-	return "lock{%;} dec{<imodesuffix>}\t%0";
+	return "lock{%;} %K2dec{<imodesuffix>}\t%0";
     }
 
   if (x86_maybe_negate_const_int (&operands[1], <MODE>mode))
-    return "lock{%;} sub{<imodesuffix>}\t{%1, %0|%0, %1}";
+    return "lock{%;} %K2sub{<imodesuffix>}\t{%1, %0|%0, %1}";
 
-  return "lock{%;} add{<imodesuffix>}\t{%1, %0|%0, %1}";
+  return "lock{%;} %K2add{<imodesuffix>}\t{%1, %0|%0, %1}";
 })
 
 (define_insn "atomic_sub<mode>"
@@ -565,15 +570,15 @@
   if (TARGET_USE_INCDEC)
     {
       if (operands[1] == const1_rtx)
-	return "lock{%;} dec{<imodesuffix>}\t%0";
+	return "lock{%;} %K2dec{<imodesuffix>}\t%0";
       if (operands[1] == constm1_rtx)
-	return "lock{%;} inc{<imodesuffix>}\t%0";
+	return "lock{%;} %K2inc{<imodesuffix>}\t%0";
     }
 
   if (x86_maybe_negate_const_int (&operands[1], <MODE>mode))
-    return "lock{%;} add{<imodesuffix>}\t{%1, %0|%0, %1}";
+    return "lock{%;} %K2add{<imodesuffix>}\t{%1, %0|%0, %1}";
 
-  return "lock{%;} sub{<imodesuffix>}\t{%1, %0|%0, %1}";
+  return "lock{%;} %K2sub{<imodesuffix>}\t{%1, %0|%0, %1}";
 })
 
 (define_insn "atomic_<logic><mode>"
@@ -585,4 +590,4 @@
 	  UNSPECV_LOCK))
    (clobber (reg:CC FLAGS_REG))]
   ""
-  "lock{%;} <logic>{<imodesuffix>}\t{%1, %0|%0, %1}")
+  "lock{%;} %K2<logic>{<imodesuffix>}\t{%1, %0|%0, %1}")