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| author | hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-03-27 18:56:00 +0000 |
|---|---|---|
| committer | hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-03-27 18:56:00 +0000 |
| commit | b8cb8d5224d650672add0fb6a74d759ef12e428f (patch) | |
| tree | 6bde920e9a82430f7109eaf06eaa946470377eb2 /gcc/config/i386/sse.md | |
| parent | 76ff5588ec732019bab1fae57feceeea597eaaa7 (diff) | |
| download | gcc-b8cb8d5224d650672add0fb6a74d759ef12e428f.tar.gz | |
Split 32-byte AVX unaligned load/store.
gcc/
2011-03-27 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/i386.c (flag_opts): Add -mavx256-split-unaligned-load
and -mavx256-split-unaligned-store.
(ix86_option_override_internal): Split 32-byte AVX unaligned
load/store by default.
(ix86_avx256_split_vector_move_misalign): New.
(ix86_expand_vector_move_misalign): Use it.
* config/i386/i386.opt: Add -mavx256-split-unaligned-load and
-mavx256-split-unaligned-store.
* config/i386/sse.md (*avx_mov<mode>_internal): Verify unaligned
256bit load/store. Generate unaligned store on misaligned memory
operand.
(*avx_movu<ssemodesuffix><avxmodesuffix>): Verify unaligned
256bit load/store.
(*avx_movdqu<avxmodesuffix>): Likewise.
* doc/invoke.texi: Document -mavx256-split-unaligned-load and
-mavx256-split-unaligned-store.
gcc/testsuite/
2011-03-27 H.J. Lu <hongjiu.lu@intel.com>
* gcc.target/i386/avx256-unaligned-load-1.c: New.
* gcc.target/i386/avx256-unaligned-load-2.c: Likewise.
* gcc.target/i386/avx256-unaligned-load-3.c: Likewise.
* gcc.target/i386/avx256-unaligned-load-4.c: Likewise.
* gcc.target/i386/avx256-unaligned-load-5.c: Likewise.
* gcc.target/i386/avx256-unaligned-load-6.c: Likewise.
* gcc.target/i386/avx256-unaligned-load-7.c: Likewise.
* gcc.target/i386/avx256-unaligned-store-1.c: Likewise.
* gcc.target/i386/avx256-unaligned-store-2.c: Likewise.
* gcc.target/i386/avx256-unaligned-store-3.c: Likewise.
* gcc.target/i386/avx256-unaligned-store-4.c: Likewise.
* gcc.target/i386/avx256-unaligned-store-5.c: Likewise.
* gcc.target/i386/avx256-unaligned-store-6.c: Likewise.
* gcc.target/i386/avx256-unaligned-store-7.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@171578 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/i386/sse.md')
| -rw-r--r-- | gcc/config/i386/sse.md | 42 |
1 files changed, 37 insertions, 5 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 70a0b344bdf..de11f7362ec 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -203,19 +203,35 @@ return standard_sse_constant_opcode (insn, operands[1]); case 1: case 2: + if (GET_MODE_ALIGNMENT (<MODE>mode) == 256 + && ((TARGET_AVX256_SPLIT_UNALIGNED_STORE + && misaligned_operand (operands[0], <MODE>mode)) + || (TARGET_AVX256_SPLIT_UNALIGNED_LOAD + && misaligned_operand (operands[1], <MODE>mode)))) + gcc_unreachable (); switch (get_attr_mode (insn)) { case MODE_V8SF: case MODE_V4SF: - return "vmovaps\t{%1, %0|%0, %1}"; + if (misaligned_operand (operands[0], <MODE>mode) + || misaligned_operand (operands[1], <MODE>mode)) + return "vmovups\t{%1, %0|%0, %1}"; + else + return "vmovaps\t{%1, %0|%0, %1}"; case MODE_V4DF: case MODE_V2DF: - if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) + if (misaligned_operand (operands[0], <MODE>mode) + || misaligned_operand (operands[1], <MODE>mode)) + return "vmovupd\t{%1, %0|%0, %1}"; + else if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) return "vmovaps\t{%1, %0|%0, %1}"; else return "vmovapd\t{%1, %0|%0, %1}"; default: - if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) + if (misaligned_operand (operands[0], <MODE>mode) + || misaligned_operand (operands[1], <MODE>mode)) + return "vmovdqu\t{%1, %0|%0, %1}"; + else if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) return "vmovaps\t{%1, %0|%0, %1}"; else return "vmovdqa\t{%1, %0|%0, %1}"; @@ -400,7 +416,15 @@ UNSPEC_MOVU))] "AVX_VEC_FLOAT_MODE_P (<MODE>mode) && !(MEM_P (operands[0]) && MEM_P (operands[1]))" - "vmovu<ssemodesuffix>\t{%1, %0|%0, %1}" +{ + if (GET_MODE_ALIGNMENT (<MODE>mode) == 256 + && ((TARGET_AVX256_SPLIT_UNALIGNED_STORE + && misaligned_operand (operands[0], <MODE>mode)) + || (TARGET_AVX256_SPLIT_UNALIGNED_LOAD + && misaligned_operand (operands[1], <MODE>mode)))) + gcc_unreachable (); + return "vmovu<ssemodesuffix>\t{%1, %0|%0, %1}"; +} [(set_attr "type" "ssemov") (set_attr "movu" "1") (set_attr "prefix" "vex") @@ -459,7 +483,15 @@ [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "xm,x")] UNSPEC_MOVU))] "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" - "vmovdqu\t{%1, %0|%0, %1}" +{ + if (GET_MODE_ALIGNMENT (<MODE>mode) == 256 + && ((TARGET_AVX256_SPLIT_UNALIGNED_STORE + && misaligned_operand (operands[0], <MODE>mode)) + || (TARGET_AVX256_SPLIT_UNALIGNED_LOAD + && misaligned_operand (operands[1], <MODE>mode)))) + gcc_unreachable (); + return "vmovdqu\t{%1, %0|%0, %1}"; +} [(set_attr "type" "ssemov") (set_attr "movu" "1") (set_attr "prefix" "vex") |