diff options
| author | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-10-06 17:12:36 +0000 |
|---|---|---|
| committer | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-10-06 17:12:36 +0000 |
| commit | 12cbfa26a81ff3cc7e644ca9bbefde2b396ba64b (patch) | |
| tree | 79d2344f83536551f5ddcd1e7afd6976092174f1 /gcc/config/i386/sse.md | |
| parent | 1735c47d7b5686d26af724799db78d40a6763269 (diff) | |
| download | gcc-12cbfa26a81ff3cc7e644ca9bbefde2b396ba64b.tar.gz | |
i386: Add AVX2 support to ix86_expand_vshuffle.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@179624 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/i386/sse.md')
| -rw-r--r-- | gcc/config/i386/sse.md | 31 |
1 files changed, 18 insertions, 13 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 88f4d6c1f19..bf1d448f84d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -230,19 +230,16 @@ (V4SF "V4SF") (V2DF "V2DF") (TI "TI")]) -;; All 128bit vector modes -(define_mode_attr sseshuffint - [(V16QI "V16QI") (V8HI "V8HI") - (V4SI "V4SI") (V2DI "V2DI") - (V4SF "V4SI") (V2DF "V2DI")]) - ;; Mapping of vector float modes to an integer mode of the same size (define_mode_attr sseintvecmode [(V8SF "V8SI") (V4DF "V4DI") (V4SF "V4SI") (V2DF "V2DI") (V4DF "V4DI") (V8SF "V8SI") (V8SI "V8SI") (V4DI "V4DI") - (V4SI "V4SI") (V2DI "V2DI")]) + (V4SI "V4SI") (V2DI "V2DI") + (V16HI "V16HI") (V8HI "V8HI") + (V32QI "V32QI") (V16QI "V16QI") + ]) ;; Mapping of vector modes to a vector mode of double size (define_mode_attr ssedoublevecmode @@ -6226,12 +6223,20 @@ DONE; }) +;; ??? Irritatingly, the 256-bit VPSHUFB only shuffles within the 128-bit +;; lanes. For now, we don't try to support V32QI or V16HImode. So we +;; don't want to use VI_AVX2. +(define_mode_iterator VSHUFFLE_AVX2 + [V16QI V8HI V4SI V2DI V4SF V2DF + (V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2") + (V8SF "TARGET_AVX2") (V4DF "TARGET_AVX2")]) + (define_expand "vshuffle<mode>" - [(match_operand:V_128 0 "register_operand" "") - (match_operand:V_128 1 "register_operand" "") - (match_operand:V_128 2 "register_operand" "") - (match_operand:<sseshuffint> 3 "register_operand" "")] - "TARGET_SSSE3 || TARGET_AVX" + [(match_operand:VSHUFFLE_AVX2 0 "register_operand" "") + (match_operand:VSHUFFLE_AVX2 1 "register_operand" "") + (match_operand:VSHUFFLE_AVX2 2 "register_operand" "") + (match_operand:<sseintvecmode> 3 "register_operand" "")] + "TARGET_SSSE3 || TARGET_AVX || TARGET_XOP" { ix86_expand_vshuffle (operands); DONE; @@ -12397,7 +12402,7 @@ (set_attr "prefix" "vex") (set_attr "mode" "TI")]) -(define_insn "*vec_concat<mode>_avx" +(define_insn "avx_vec_concat<mode>" [(set (match_operand:V_256 0 "register_operand" "=x,x") (vec_concat:V_256 (match_operand:<ssehalfvecmode> 1 "register_operand" "x,x") |