Support AVX Programming Reference (June, 2010).

gcc/

2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* config/i386/cpuid.h (bit_F16C): New.
	(bit_RDRND): Likewise.
	(bit_FSGSBASE): Likewise.

	* config/i386/i386-builtin-types.def: Add
	"DEF_FUNCTION_TYPE (UINT16)", function types for
	float16 <-> float conversions and
	"DEF_FUNCTION_TYPE (VOID, UINT64)".

	* config/i386/i386-c.c (ix86_target_macros_internal): Support
	OPTION_MASK_ISA_FSGSBASE, OPTION_MASK_ISA_RDRND and
	OPTION_MASK_ISA_F16C.

	* config/i386/i386.c (OPTION_MASK_ISA_FSGSBASE_SET): New.
	(OPTION_MASK_ISA_RDRND_SET): Likewise.
	(OPTION_MASK_ISA_F16C_SET): Likewise.
	(OPTION_MASK_ISA_FSGSBASE_UNSET): Likewise.
	(OPTION_MASK_ISA_RDRND_UNSET): Likewise.
	(OPTION_MASK_ISA_F16C_UNSET): Likewise.
	(OPTION_MASK_ISA_AVX_UNSET): Add OPTION_MASK_ISA_F16C_UNSET.
	(ix86_handle_option): Handle OPT_mfsgsbase, OPT_mrdrnd and
	OPT_mf16c.
	(ix86_target_string): Support -mfsgsbase, -mrdrnd and -mf16c.
	(pta_flags): Add PTA_FSGSBASE, PTA_RDRND and PTA_F16C.
	(override_options): Handle them.
	(ix86_valid_target_attribute_inner_p): Handle fsgsbase, rdrnd
	and f16c.
	(ix86_builtins): Add IX86_BUILTIN_RDFSBASE32,
	IX86_BUILTIN_RDFSBASE64, IX86_BUILTIN_RDGSBASE32,
	IX86_BUILTIN_RDGSBASE64, IX86_BUILTIN_WRFSBASE32,
	IX86_BUILTIN_WRFSBASE64, IX86_BUILTIN_WRGSBASE32,
	IX86_BUILTIN_WRGSBASE64, IX86_BUILTIN_RDRAND16,
	IX86_BUILTIN_RDRAND32, IX86_BUILTIN_RDRAND64,
	IX86_BUILTIN_CVTPH2PS, IX86_BUILTIN_CVTPH2PS256,
	IX86_BUILTIN_CVTPS2PH and IX86_BUILTIN_CVTPS2PH256.
	(bdesc_args): Likewise.
	(ix86_expand_args_builtin): Handle V8SF_FTYPE_V8HI,
	V4SF_FTYPE_V8HI, V8HI_FTYPE_V8SF_INT and V8HI_FTYPE_V4SF_INT.
	(ix86_expand_special_args_builtin): Handle VOID_FTYPE_UINT64,
	VOID_FTYPE_UNSIGNED, UNSIGNED_FTYPE_VOID and UINT16_FTYPE_VOID.
	Handle non-memory store.

	* config/i386/i386.h (TARGET_FSGSBASE): New.
	(TARGET_RDRND): Likewise.
	(TARGET_F12C): Likewise.

	* config/i386/i386.md (UNSPEC_VCVTPH2PS): New.
	(UNSPEC_VCVTPS2PH): Likewise.
	(UNSPECV_RDFSBASE): Likewise.
	(UNSPECV_RDGSBASE): Likewise.
	(UNSPECV_WRFSBASE): Likewise.
	(UNSPECV_WRGSBASE): Likewise.
	(UNSPECV_RDRAND): Likewise.
	(rdfsbase<mode>): Likewise.
	(rdgsbase<mode>): Likewise.
	(wrfsbase<mode>): Likewise.
	(wrgsbase<mode>): Likewise.
	(rdrand<mode>): Likewise.

	* config/i386/i386.opt: Add -mfsgsbase, -mrdrnd and -mf16c.

	* config/i386/immintrin.h (_rdrand_u16): New.
	(_rdrand_u32): Likewise.
	(_readfsbase_u32): Likewise.
	(_readfsbase_u64): Likewise.
	(_readgsbase_u32): Likewise.
	(_readgsbase_u64): Likewise.
	(_writefsbase_u32): Likewise.
	(_writefsbase_u64): Likewise.
	(_writegsbase_u32): Likewise.
	(_writegsbase_u64): Likewise.
	(_rdrand_u64): Likewise.
	(_cvtsh_ss): Likewise.
	(_mm_cvtph_ps): Likewise.
	(_mm256_cvtph_ps): Likewise.
	(_cvtss_sh): Likewise.
	(_mm_cvtps_ph): Likewise.
	(_mm256_cvtps_ph): Likewise.

	* config/i386/sse.md (vcvtph2ps): New.
	(*vcvtph2ps_load): Likewise.
	(vcvtph2ps256): Likewise.
	(vcvtps2ph): Likewise.
	(*vcvtps2ph): Likewise.
	(*vcvtps2ph_store): Likewise.
	(vcvtps2ph256): Likewise.

	* doc/extend.texi: Document FSGSBASE and RDRND built-in functions.

	* doc/invoke.texi: Document -mfsgsbase, -mrdrnd and -mf16c.

gcc/testsuite/

2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* g++.dg/other/i386-2.C: Add -mfsgsbase -mrdrnd -mf16c.
	* g++.dg/other/i386-3.C: Likewise.
	* gcc.target/i386/sse-12.c: Likewise.

	* gcc.target/i386/f16c-check.h: New.
	* gcc.target/i386/rdfsbase-1.c: Likewise.
	* gcc.target/i386/rdfsbase-2.c: Likewise.
	* gcc.target/i386/rdgsbase-1.c: Likewise.
	* gcc.target/i386/rdgsbase-2.c: Likewise.
	* gcc.target/i386/rdrand-1.c: Likewise.
	* gcc.target/i386/rdrand-2.c: Likewise.
	* gcc.target/i386/rdrand-3.c: Likewise.
	* gcc.target/i386/vcvtph2ps-1.c: Likewise.
	* gcc.target/i386/vcvtph2ps-2.c: Likewise.
	* gcc.target/i386/vcvtph2ps-3.c: Likewise.
	* gcc.target/i386/vcvtps2ph-1.c: Likewise.
	* gcc.target/i386/vcvtps2ph-2.c: Likewise.
	* gcc.target/i386/vcvtps2ph-3.c: Likewise.
	* gcc.target/i386/wrfsbase-1.c: Likewise.
	* gcc.target/i386/wrfsbase-2.c: Likewise.
	* gcc.target/i386/wrgsbase-1.c: Likewise.
	* gcc.target/i386/wrgsbase-2.c: Likewise.

	* gcc.target/i386/sse-13.c: Add -mfsgsbase -mrdrnd -mf16c.
	(__builtin_ia32_vcvtps2ph): New.
	(__builtin_ia32_vcvtps2ph256): Likewise.

	* gcc.target/i386/sse-14.c: Add -mfsgsbase -mrdrnd -mf16c.
	Test _cvtss_sh, _mm_cvtps_ph and _mm256_cvtps_ph.

	* gcc.target/i386/sse-22.c: Add fsgsbase,rdrnd,f16c.
	Test _cvtss_sh, _mm_cvtps_ph and _mm256_cvtps_ph.

	* gcc.target/i386/sse-23.c (__builtin_ia32_vcvtps2ph): New.
	(__builtin_ia32_vcvtps2ph256): Likewise.
	Add fsgsbase,rdrnd,f16c.

	* lib/target-supports.exp (check_effective_target_f16c): New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161855 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 144 insertions, 0 deletions

diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index 7a2b9b9c63e..3e69060700a 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -56,4 +56,148 @@
 #include <avxintrin.h>
 #endif
 
+#ifdef __RDRND__
+extern __inline unsigned short
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_rdrand_u16 (void)
+{
+  return __builtin_ia32_rdrand16 ();
+}
+
+extern __inline unsigned int
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_rdrand_u32 (void)
+{
+  return __builtin_ia32_rdrand32 ();
+}
+#endif /* __RDRND__ */
+
+#ifdef  __x86_64__
+#ifdef __FSGSBASE__
+extern __inline unsigned int
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_readfsbase_u32 (void)
+{
+  return __builtin_ia32_rdfsbase32 ();
+}
+
+extern __inline unsigned long long
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_readfsbase_u64 (void)
+{
+  return __builtin_ia32_rdfsbase64 ();
+}
+
+extern __inline unsigned int
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_readgsbase_u32 (void)
+{
+  return __builtin_ia32_rdgsbase32 ();
+}
+
+extern __inline unsigned long long
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_readgsbase_u64 (void)
+{
+  return __builtin_ia32_rdgsbase64 ();
+}
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_writefsbase_u32 (unsigned int __B)
+{
+  __builtin_ia32_wrfsbase32 (__B);
+}
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_writefsbase_u64 (unsigned long long __B)
+{
+  __builtin_ia32_wrfsbase64 (__B);
+}
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_writegsbase_u32 (unsigned int __B)
+{
+  __builtin_ia32_wrgsbase32 (__B);
+}
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_writegsbase_u64 (unsigned long long __B)
+{
+  __builtin_ia32_wrgsbase64 (__B);
+}
+#endif /* __FSGSBASE__ */
+
+#ifdef __RDRND__
+extern __inline unsigned long long
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_rdrand_u64 (void)
+{
+  return __builtin_ia32_rdrand64 ();
+}
+#endif /* __RDRND__ */
+#endif /* __x86_64__  */
+
+#ifdef __F16C__
+extern __inline float __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_cvtsh_ss (unsigned short __S)
+{
+  __v8hi __H = __extension__ (__v8hi){ __S, 0, 0, 0, 0, 0, 0, 0 };
+  __v4sf __A = __builtin_ia32_vcvtph2ps (__H);
+  return __builtin_ia32_vec_ext_v4sf (__A, 0);
+}
+
+extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtph_ps (__m128i __A)
+{
+  return (__m128) __builtin_ia32_vcvtph2ps ((__v8hi) __A);
+}
+
+extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtph_ps (__m128i __A)
+{
+  return (__m256) __builtin_ia32_vcvtph2ps256 ((__v8hi) __A);
+}
+
+#ifdef __OPTIMIZE__
+extern __inline unsigned short __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_cvtss_sh (float __F, const int __I)
+{
+  __v4sf __A =  __extension__ (__v4sf){ __F, 0, 0, 0 };
+  __v8hi __H = __builtin_ia32_vcvtps2ph (__A, __I);
+  return (unsigned short) __builtin_ia32_vec_ext_v8hi (__H, 0);
+}
+
+extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtps_ph (__m128 __A, const int __I)
+{
+  return (__m128i) __builtin_ia32_vcvtps2ph ((__v4sf) __A, __I);
+}
+
+extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtps_ph (__m256 __A, const int __I)
+{
+  return (__m128i) __builtin_ia32_vcvtps2ph256 ((__v8sf) __A, __I);
+}
+#else
+#define _cvtss_sh(__F, __I)						\
+  (__extension__ 							\
+   ({									\
+      __v4sf __A =  __extension__ (__v4sf){ __F, 0, 0, 0 };		\
+      __v8hi __H = __builtin_ia32_vcvtps2ph (__A, __I);			\
+      (unsigned short) __builtin_ia32_vec_ext_v8hi (__H, 0);		\
+    }))
+
+#define _mm_cvtps_ph(A, I) \
+  ((__m128i) __builtin_ia32_vcvtps2ph ((__v4sf)(__m128) A, (int) (I)))
+
+#define _mm256_cvtps_ph(A, I) \
+  ((__m128i) __builtin_ia32_vcvtps2ph256 ((__v8sf)(__m256) A, (int) (I)))
+#endif
+
+#endif /* __F16C__ */
+
 #endif /* _IMMINTRIN_H_INCLUDED */