2009-11-04 Harsha Jagasia <harsha.jagasia@amd.com>

            Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>

        * doc/invoke.texi (-mlwp): Add documentation.
        * doc/extend.texi (x86 intrinsics): Add LWP intrinsics.
        * config.gcc (i[34567]86-*-*): Include lwpintrin.h.
        (x86_64-*-*): Ditto.
        * config/i386/lwpintrin.h: New file, provide x86 compiler
        intrinisics for LWP.
        * config/i386/cpuid.h (bit_LWP): Define LWP bit.
        * config/i386/x86intrin.h: Add LWP check and lwpintrin.h.
        * config/i386/i386-c.c (ix86_target_macros_internal): Check
        ISA_FLAG for LWP. 
        * config/i386/i386.h (TARGET_LWP): New macro for LWP.
        * config/i386/i386.opt (-mlwp): New switch for LWP support.
        * config/i386/i386.c (OPTION_MASK_ISA_LWP_SET): New.
        (OPTION_MASK_ISA_LWP_UNSET): New.       
        (ix86_handle_option): Handle -mlwp.
        (isa_opts): Handle -mlwp.
        (enum pta_flags): Add PTA_LWP.
        (override_options): Add LWP support.
        (IX86_BUILTIN_LLWPCB16): New for LWP intrinsic.
        (IX86_BUILTIN_LLWPCB32): Ditto.
        (IX86_BUILTIN_LLWPCB64): Ditto.
        (IX86_BUILTIN_SLWPCB16): Ditto.
        (IX86_BUILTIN_SLWPCB32): Ditto.
        (IX86_BUILTIN_SLWPCB64): Ditto.
        (IX86_BUILTIN_LWPVAL16): Ditto.
        (IX86_BUILTIN_LWPVAL32): Ditto.
        (IX86_BUILTIN_LWPVAL64): Ditto.
        (IX86_BUILTIN_LWPINS16): Ditto.
        (IX86_BUILTIN_LWPINS32): Ditto.
        (IX86_BUILTIN_LWPINS64): Ditto.
        (enum  ix86_special_builtin_type): Add LWP intrinsic support.
        (builtin_description): Ditto.
        (ix86_init_mmx_sse_builtins): Ditto.
        (ix86_expand_special_args_builtin): Ditto.
        * config/i386/i386.md (UNSPEC_LLWP_INTRINSIC): Add new UNSPEC
        for LWP support.
        (UNSPEC_SLWP_INTRINSIC): Ditto.
        (UNSPECV_LWPVAL_INTRINSIC): Ditto.
        (UNSPECV_LWPINS_INTRINSIC): Ditto.
        (lwp_llwpcbhi1): New lwp pattern.
        (lwp_llwpcbsi1): Ditto.
        (lwp_llwpcbdi1): Ditto.
        (lwp_slwpcbhi1): Ditto.
        (lwp_slwpcbsi1): Ditto.
        (lwp_slwpcbdi1): Ditto.
        (lwp_lwpvalhi3): Ditto.
        (lwp_lwpvalsi3): Ditto.
        (lwp_lwpvaldi3): Ditto.
        (lwp_lwpinshi3): Ditto.
        (lwp_lwpinssi3): Ditto.
        (lwp_lwpinsdi3): Ditto.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@153917 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 119 insertions, 1 deletions

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 0e051cdee6b..c011d9b4347 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -204,6 +204,10 @@
    (UNSPEC_XOP_TRUEFALSE	152)
    (UNSPEC_XOP_PERMUTE		153)
    (UNSPEC_FRCZ			154)
+   (UNSPEC_LLWP_INTRINSIC	155)
+   (UNSPEC_SLWP_INTRINSIC	156)
+   (UNSPECV_LWPVAL_INTRINSIC	157)
+   (UNSPECV_LWPINS_INTRINSIC	158)
 
    ; For AES support
    (UNSPEC_AESENC		159)
@@ -353,7 +357,7 @@
    fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint,
    sselog,sselog1,sseiadd,sseiadd1,sseishft,sseimul,
    sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,ssediv,sseins,
-   ssemuladd,sse4arg,
+   ssemuladd,sse4arg,lwp,
    mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
   (const_string "other"))
 
@@ -21838,6 +21842,120 @@
   [(set_attr "type" "other")
    (set_attr "length" "3")])
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; LWP instructions
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(define_insn "lwp_llwpcbhi1"
+  [(unspec [(match_operand:HI 0 "register_operand" "r")]
+  	   UNSPEC_LLWP_INTRINSIC)]
+  "TARGET_LWP"
+  "llwpcb\t%0"
+  [(set_attr "type" "lwp")
+   (set_attr "mode" "HI")])
+
+(define_insn "lwp_llwpcbsi1"
+  [(unspec [(match_operand:SI 0 "register_operand" "r")]
+  	   UNSPEC_LLWP_INTRINSIC)]
+  "TARGET_LWP"
+  "llwpcb\t%0"
+  [(set_attr "type" "lwp")
+   (set_attr "mode" "SI")])
+
+(define_insn "lwp_llwpcbdi1"
+  [(unspec [(match_operand:DI 0 "register_operand" "r")]
+  	   UNSPEC_LLWP_INTRINSIC)]
+  "TARGET_LWP"
+  "llwpcb\t%0"
+  [(set_attr "type" "lwp")
+   (set_attr "mode" "DI")])
+
+(define_insn "lwp_slwpcbhi1"
+  [(unspec [(match_operand:HI 0 "register_operand" "r")]
+  	   UNSPEC_SLWP_INTRINSIC)]
+  "TARGET_LWP"
+  "slwpcb\t%0"
+  [(set_attr "type" "lwp")
+   (set_attr "mode" "HI")])
+
+(define_insn "lwp_slwpcbsi1"
+  [(unspec [(match_operand:SI 0 "register_operand" "r")]
+  	   UNSPEC_SLWP_INTRINSIC)]
+  "TARGET_LWP"
+  "slwpcb\t%0"
+  [(set_attr "type" "lwp")
+   (set_attr "mode" "SI")])
+
+(define_insn "lwp_slwpcbdi1"
+  [(unspec [(match_operand:DI 0 "register_operand" "r")]
+  	   UNSPEC_SLWP_INTRINSIC)]
+  "TARGET_LWP"
+  "slwpcb\t%0"
+  [(set_attr "type" "lwp")
+   (set_attr "mode" "DI")])
+
+(define_insn "lwp_lwpvalhi3"
+  [(unspec_volatile [(match_operand:HI 0 "register_operand" "r")
+  	   	     (match_operand:SI 1 "nonimmediate_operand" "rm")
+	   	     (match_operand:HI 2 "const_int_operand" "")]
+  	   	    UNSPECV_LWPVAL_INTRINSIC)]
+  "TARGET_LWP"
+  "lwpval\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "type" "lwp")
+   (set_attr "mode" "HI")])
+
+(define_insn "lwp_lwpvalsi3"
+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
+    	    	     (match_operand:SI 1 "nonimmediate_operand" "rm")
+	    	     (match_operand:SI 2 "const_int_operand" "")]
+		    UNSPECV_LWPVAL_INTRINSIC)]
+  "TARGET_LWP"
+  "lwpval\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "type" "lwp")
+   (set_attr "mode" "SI")])
+
+(define_insn "lwp_lwpvaldi3"
+  [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
+  		     (match_operand:SI 1 "nonimmediate_operand" "rm")
+		     (match_operand:SI 2 "const_int_operand" "")]
+		    UNSPECV_LWPVAL_INTRINSIC)]
+  "TARGET_LWP"
+  "lwpval\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "type" "lwp")
+   (set_attr "mode" "DI")])
+
+(define_insn "lwp_lwpinshi3"
+  [(unspec_volatile [(match_operand:HI 0 "register_operand" "r")
+  		     (match_operand:SI 1 "nonimmediate_operand" "rm")
+		     (match_operand:HI 2 "const_int_operand" "")]
+		    UNSPECV_LWPINS_INTRINSIC)]
+  "TARGET_LWP"
+  "lwpins\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "type" "lwp")
+   (set_attr "mode" "HI")])
+
+(define_insn "lwp_lwpinssi3"
+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
+  		     (match_operand:SI 1 "nonimmediate_operand" "rm")
+		     (match_operand:SI 2 "const_int_operand" "")]
+		    UNSPECV_LWPINS_INTRINSIC)]
+  "TARGET_LWP"
+  "lwpins\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "type" "lwp")
+   (set_attr "mode" "SI")])
+
+(define_insn "lwp_lwpinsdi3"
+  [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
+  		     (match_operand:SI 1 "nonimmediate_operand" "rm")
+		     (match_operand:SI 2 "const_int_operand" "")]
+		    UNSPECV_LWPINS_INTRINSIC)]
+  "TARGET_LWP"
+  "lwpins\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "type" "lwp")
+   (set_attr "mode" "DI")])
+
 (include "mmx.md")
 (include "sse.md")
 (include "sync.md")