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| author | Uros Bizjak <uros@gcc.gnu.org> | 2016-06-13 23:34:07 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2016-06-13 23:34:07 +0200 |
| commit | 385c7747b78f0e178666fb7f376d21389a3f0bb8 (patch) | |
| tree | c7b6909eb3ebaf242aa655314fa820d26e2c5b3a /gcc/config/i386/i386.md | |
| parent | 85ecd05c26d107921b166374dd77c40a393312c8 (diff) | |
| download | gcc-385c7747b78f0e178666fb7f376d21389a3f0bb8.tar.gz | |
i386-builtin-types.def (INT_FTYPE_FLOAT128): New function type.
* config/i386/i386-builtin-types.def (INT_FTYPE_FLOAT128):
New function type.
* config/i386/i386.c (enum ix86_builtins) [IX86_BUILTIN_SIGNBITQ]: New.
(ix86_init_builtins): Add __builtin_signbitq function.
(ix86_expand_args_builtin): Handle INT_FTYPE_FLOAT128.
(ix86_expand_builtin): Handle IX86_BUILTIN_SIGNBITQ.
* config/i386/i386.md (signbittf2): New expander.
* config/i386/sse.md (ptesttf2): New insn pattern.
* doc/extend.texi (x86 Built-in Functions): Document
__builtin_signbitq.
libgcc/ChangeLog:
* config.host (i[34567]86-*-* | x86_64-*-*): Always include
i386/${host_address}/t-softfp in tmake_file.
* config/i386/32/t-softfp: Update comment for __builtin_copysignq.
* config/i386/32/tf-signs.c: Add __signbittf2 fallback function.
* config/i386/64/t-softfp: New file.
* config/i386/64/tf-signs.c: Ditto.
* config/i386/libgcc-bsd.ver: Add __signbittf2.
* config/i386/libgcc-glibc.ver: Ditto.
* config/i386/libgcc-sol2.ver: Ditto.
testsuite/ChangeLog:
* gcc.target/i386/float128-3.c: New test.
* gcc.target/i386/quad-sse4.c: Ditto.
* gcc.target/i386/quad-sse.c: Use -msse instead of -msse2.
Update scan strings.
From-SVN: r237415
Diffstat (limited to 'gcc/config/i386/i386.md')
| -rw-r--r-- | gcc/config/i386/i386.md | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 86837525628..e69a7e44267 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -16198,6 +16198,22 @@ DONE; }) +(define_expand "signbittf2" + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:TF 1 "register_operand"))] + "TARGET_SSE4_1" +{ + rtx mask = ix86_build_signbit_mask (TFmode, 0, 0); + rtx scratch = gen_reg_rtx (QImode); + + emit_insn (gen_ptesttf2 (operands[1], mask)); + ix86_expand_setcc (scratch, NE, + gen_rtx_REG (CCZmode, FLAGS_REG), const0_rtx); + + emit_insn (gen_zero_extendqisi2 (operands[0], scratch)); + DONE; +}) + (define_expand "signbitxf2" [(use (match_operand:SI 0 "register_operand")) (use (match_operand:XF 1 "register_operand"))] |