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| author | Uros Bizjak <ubizjak@gmail.com> | 2018-09-26 17:17:32 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2018-09-26 17:17:32 +0200 |
| commit | 2202b162bbb3f0e300db716c67f67e8c2e4a92c0 (patch) | |
| tree | a6218fb783e22dab05d9f9568c2c2acf6a54dc88 /gcc/config/i386/i386.h | |
| parent | dd554b787d0280566e891dba9e19dd718e68d42a (diff) | |
| download | gcc-2202b162bbb3f0e300db716c67f67e8c2e4a92c0.tar.gz | |
i386.h (enum reg_class): Remove FP_TOP_SSE_REGS and FP_SECOND_SSE_REGS.
* config/i386/i386.h (enum reg_class): Remove FP_TOP_SSE_REGS
and FP_SECOND_SSE_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
* config/i386/i386.c (ix86_preferred_reload_class) Do not handle
FP_TOP_SSE_REGS and FP_SECOND_SSE_REGS classes.
(ix86_preferred_output_reload_class): Ditto.
* config/i386/i386.md (fix_trunc<mode>_i387_fisttp): Change "=&1f"
clobber constraint to "=&f".
(fix_truncdi_i387): Ditto.
(lrintxfdi2): Ditto.
(fistdi2_<rounding>): Ditto.
(fpremxf4_i387): Change "=u" constraint to "=f".
(fprem1xf4_i387): Ditto.
(sincosxf3): Ditto.
(fptanxf4_i387): Ditto.
(fxtractxf3_i387): Ditto.
(fscalexf4_i387): Ditto.
(atan2xf3): Change "u" constraint to "f".
(fyl2xxf3_i387): Ditto.
(fyl2xp1xf3_i387): Ditto.
From-SVN: r264648
Diffstat (limited to 'gcc/config/i386/i386.h')
| -rw-r--r-- | gcc/config/i386/i386.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index f96f864b810..6445ee5d50a 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1337,8 +1337,6 @@ enum reg_class SSE_REGS, ALL_SSE_REGS, MMX_REGS, - FP_TOP_SSE_REGS, - FP_SECOND_SSE_REGS, FLOAT_SSE_REGS, FLOAT_INT_REGS, INT_SSE_REGS, @@ -1398,8 +1396,6 @@ enum reg_class "SSE_REGS", \ "ALL_SSE_REGS", \ "MMX_REGS", \ - "FP_TOP_SSE_REGS", \ - "FP_SECOND_SSE_REGS", \ "FLOAT_SSE_REGS", \ "FLOAT_INT_REGS", \ "INT_SSE_REGS", \ @@ -1438,8 +1434,6 @@ enum reg_class { 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \ { 0x1fe00000, 0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \ { 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \ -{ 0x1fe00100, 0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \ -{ 0x1fe00200, 0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \ { 0x1fe0ff00, 0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \ { 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \ { 0x1ff100ff, 0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \ |