diff options
| author | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-05-30 17:18:25 +0000 |
|---|---|---|
| committer | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-05-30 17:18:25 +0000 |
| commit | c8bc21975193413ddda62f7aac988326e9846c58 (patch) | |
| tree | f12efd36a58a9af8380bfbc533ceb787e1f9949d /gcc/config/i386/constraints.md | |
| parent | 1b144f1382f9ce9f65527340cf4d29703c95949d (diff) | |
| download | gcc-c8bc21975193413ddda62f7aac988326e9846c58.tar.gz | |
PR target/80833
* config/i386/constraints.md (Yd): New constraint.
(Ye): Ditto.
* config/i386/i386.md (*movti_internal): Add (?r, Ye)
and (?Yd, r) alternatives. Update insn attributes.
* config/i386/i386.md (*movti_internal): Add (?r, *Ye)
and (?*Yd, r) alternatives. Update insn attributes.
(double-mode inter-unit splitters): Add new GR<->XMM splitters.
testsuite/ChangeLog:
PR target/80833
* gcc.target/i386/pr80833-1.c: New test.
* gcc.target/i386/pr80833-2.c: Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248691 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/i386/constraints.md')
| -rw-r--r-- | gcc/config/i386/constraints.md | 26 |
1 files changed, 24 insertions, 2 deletions
diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index 816704fd2e1..f94e274358b 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -102,18 +102,24 @@ ;; c SSE inter-unit conversions enabled ;; i SSE2 inter-unit moves to SSE register enabled ;; j SSE2 inter-unit moves from SSE register enabled +;; d any EVEX encodable SSE register for AVX512BW target or any SSE register +;; for SSE4_1 target, when inter-unit moves to SSE register are enabled +;; e any EVEX encodable SSE register for AVX512BW target or any SSE register +;; for SSE4_1 target, when inter-unit moves from SSE register are enabled ;; m MMX inter-unit moves to MMX register enabled ;; n MMX inter-unit moves from MMX register enabled +;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled ;; a Integer register when zero extensions with AND are disabled ;; b Any register that can be used as the GOT base when calling ;; ___tls_get_addr: that is, any general register except EAX ;; and ESP, for -fno-plt if linker supports it. Otherwise, ;; EBX. -;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled ;; f x87 register when 80387 floating point arithmetic is enabled ;; r SSE regs not requiring REX prefix when prefixes avoidance is enabled ;; and all SSE regs otherwise -;; h EVEX encodable SSE register with number factor of four +;; v any EVEX encodable SSE register for AVX512VL target, +;; otherwise any SSE register +;; h EVEX encodable SSE register with number factor of four (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS" "First SSE register (@code{%xmm0}).") @@ -130,6 +136,22 @@ "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC ? ALL_SSE_REGS : NO_REGS" "@internal Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.") +(define_register_constraint "Yd" + "TARGET_INTER_UNIT_MOVES_TO_VEC + ? (TARGET_AVX512BW + ? ALL_SSE_REGS + : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) + : NO_REGS" + "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.") + +(define_register_constraint "Ye" + "TARGET_INTER_UNIT_MOVES_FROM_VEC + ? (TARGET_AVX512BW + ? ALL_SSE_REGS + : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) + : NO_REGS" + "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.") + (define_register_constraint "Ym" "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS" "@internal Any MMX register, when inter-unit moves to vector registers are enabled.") |