* config/frv/frv.c, config/frv/frv.h, config/frv/frv.md,

	config/frv/predicates.md: Follow spelling conventions.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@122118 138bc75d-0d04-0410-961f-82ee72b054a4

4 files changed, 41 insertions, 41 deletions

diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index b8701a527d7..cc18ac036a5 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -3360,7 +3360,7 @@ frv_legitimate_address_p (enum machine_mode mode,
       break;
 
     case CONST_INT:
-      /* 12 bit immediate */
+      /* 12-bit immediate */
       if (condexec_p)
 	ret = FALSE;
       else
@@ -3411,7 +3411,7 @@ frv_legitimate_address_p (enum machine_mode mode,
 	  break;
 
 	case CONST_INT:
-          /* 12 bit immediate */
+          /* 12-bit immediate */
 	  if (condexec_p)
 	    ret = FALSE;
 	  else
@@ -9483,7 +9483,7 @@ frv_rtx_costs (rtx x,
   switch (code)
     {
     case CONST_INT:
-      /* Make 12 bit integers really cheap.  */
+      /* Make 12-bit integers really cheap.  */
       if (IN_RANGE_P (INTVAL (x), -2048, 2047))
 	{
 	  *total = 0;
diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h
index 6c53a4dbe99..ab8704f6695 100644
--- a/gcc/config/frv/frv.h
+++ b/gcc/config/frv/frv.h
@@ -1272,21 +1272,21 @@ extern enum reg_class reg_class_from_letter[];
 
 #define ZERO_P(x) (x == CONST0_RTX (GET_MODE (x)))
 
-/* 6 bit signed immediate.  */
+/* 6-bit signed immediate.  */
 #define CONST_OK_FOR_I(VALUE) IN_RANGE_P(VALUE, -32, 31)
-/* 10 bit signed immediate.  */
+/* 10-bit signed immediate.  */
 #define CONST_OK_FOR_J(VALUE) IN_RANGE_P(VALUE, -512, 511)
 /* Unused */
 #define CONST_OK_FOR_K(VALUE)  0
-/* 16 bit signed immediate.  */
+/* 16-bit signed immediate.  */
 #define CONST_OK_FOR_L(VALUE) IN_RANGE_P(VALUE, -32768, 32767)
-/* 16 bit unsigned immediate.  */
+/* 16-bit unsigned immediate.  */
 #define CONST_OK_FOR_M(VALUE)  IN_RANGE_P (VALUE, 0, 65535)
-/* 12 bit signed immediate that is negative.  */
+/* 12-bit signed immediate that is negative.  */
 #define CONST_OK_FOR_N(VALUE) IN_RANGE_P(VALUE, -2048, -1)
 /* Zero */
 #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
-/* 12 bit signed immediate that is negative.  */
+/* 12-bit signed immediate that is negative.  */
 #define CONST_OK_FOR_P(VALUE) IN_RANGE_P(VALUE, 1, 2047)
 
 /* A C expression that defines the machine-dependent operand constraint letters
diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md
index d393204216b..14c863f3c49 100644
--- a/gcc/config/frv/frv.md
+++ b/gcc/config/frv/frv.md
@@ -133,11 +133,11 @@
 ;;     than a word wide.  Constraints for these operands should use `n' rather
 ;;     than `i'.
 ;;
-;; 'I' First machine-dependent integer constant (6 bit signed ints).
-;; 'J' Second machine-dependent integer constant (10 bit signed ints).
+;; 'I' First machine-dependent integer constant (6-bit signed ints).
+;; 'J' Second machine-dependent integer constant (10-bit signed ints).
 ;; 'K' Third machine-dependent integer constant (-2048).
-;; 'L' Fourth machine-dependent integer constant (16 bit signed ints).
-;; 'M' Fifth machine-dependent integer constant (16 bit unsigned ints).
+;; 'L' Fourth machine-dependent integer constant (16-bit signed ints).
+;; 'M' Fifth machine-dependent integer constant (16-bit unsigned ints).
 ;; 'N' Sixth machine-dependent integer constant (-2047..-1).
 ;; 'O' Seventh machine-dependent integer constant (zero).
 ;; 'P' Eighth machine-dependent integer constant (1..2047).
@@ -2916,7 +2916,7 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 32 bit Integer arithmetic
+;; :: 32-bit Integer arithmetic
 ;; ::
 ;; ::::::::::::::::::::
 
@@ -2943,7 +2943,7 @@
   [(set_attr "length" "4")
    (set_attr "type" "int")])
 
-;; Signed multiplication producing 64 bit results from 32 bit inputs
+;; Signed multiplication producing 64-bit results from 32-bit inputs
 ;; Note, frv doesn't have a 32x32->32 bit multiply, but the compiler
 ;; will do the 32x32->64 bit multiply and use the bottom word.
 (define_expand "mulsidi3"
@@ -2978,7 +2978,7 @@
   [(set_attr "length" "4")
    (set_attr "type" "mul")])
 
-;; Unsigned multiplication producing 64 bit results from 32 bit inputs
+;; Unsigned multiplication producing 64-bit results from 32-bit inputs
 (define_expand "umulsidi3"
   [(set (match_operand:DI 0 "even_gpr_operand" "")
 	(mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" ""))
@@ -3051,7 +3051,7 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 64 bit Integer arithmetic
+;; :: 64-bit Integer arithmetic
 ;; ::
 ;; ::::::::::::::::::::
 
@@ -3230,7 +3230,7 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 32 bit floating point arithmetic
+;; :: 32-bit floating point arithmetic
 ;; ::
 ;; ::::::::::::::::::::
 
@@ -3325,7 +3325,7 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 64 bit floating point arithmetic
+;; :: 64-bit floating point arithmetic
 ;; ::
 ;; ::::::::::::::::::::
 
@@ -3420,7 +3420,7 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 32 bit Integer Shifts and Rotates
+;; :: 32-bit Integer Shifts and Rotates
 ;; ::
 ;; ::::::::::::::::::::
 
@@ -3475,7 +3475,7 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 64 bit Integer Shifts and Rotates
+;; :: 64-bit Integer Shifts and Rotates
 ;; ::
 ;; ::::::::::::::::::::
 
@@ -3527,11 +3527,11 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 32 Bit Integer Logical operations
+;; :: 32-Bit Integer Logical operations
 ;; ::
 ;; ::::::::::::::::::::
 
-;; Logical AND, 32 bit integers
+;; Logical AND, 32-bit integers
 (define_insn "andsi3_media"
   [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
 	(and:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
@@ -3559,7 +3559,7 @@
   ""
   "")
 
-;; Inclusive OR, 32 bit integers
+;; Inclusive OR, 32-bit integers
 (define_insn "iorsi3_media"
   [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
 	(ior:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
@@ -3587,7 +3587,7 @@
   ""
   "")
 
-;; Exclusive OR, 32 bit integers
+;; Exclusive OR, 32-bit integers
 (define_insn "xorsi3_media"
   [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
 	(xor:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
@@ -3615,7 +3615,7 @@
   ""
   "")
 
-;; One's complement, 32 bit integers
+;; One's complement, 32-bit integers
 (define_insn "one_cmplsi2_media"
   [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
 	(not:SI (match_operand:SI 1 "gpr_or_fpr_operand" "d,f")))]
@@ -3643,11 +3643,11 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 64 Bit Integer Logical operations
+;; :: 64-Bit Integer Logical operations
 ;; ::
 ;; ::::::::::::::::::::
 
-;; Logical AND, 64 bit integers
+;; Logical AND, 64-bit integers
 ;; (define_insn "anddi3"
 ;;   [(set (match_operand:DI 0 "register_operand" "=r")
 ;; 	(and:DI (match_operand:DI 1 "register_operand" "%r")
@@ -3656,7 +3656,7 @@
 ;;   "anddi3 %0,%1,%2"
 ;;   [(set_attr "length" "4")])
 
-;; Inclusive OR, 64 bit integers
+;; Inclusive OR, 64-bit integers
 ;; (define_insn "iordi3"
 ;;   [(set (match_operand:DI 0 "register_operand" "=r")
 ;; 	(ior:DI (match_operand:DI 1 "register_operand" "%r")
@@ -3665,7 +3665,7 @@
 ;;   "iordi3 %0,%1,%2"
 ;;   [(set_attr "length" "4")])
 
-;; Exclusive OR, 64 bit integers
+;; Exclusive OR, 64-bit integers
 ;; (define_insn "xordi3"
 ;;   [(set (match_operand:DI 0 "register_operand" "=r")
 ;; 	(xor:DI (match_operand:DI 1 "register_operand" "%r")
@@ -3674,7 +3674,7 @@
 ;;   "xordi3 %0,%1,%2"
 ;;   [(set_attr "length" "4")])
 
-;; One's complement, 64 bit integers
+;; One's complement, 64-bit integers
 ;; (define_insn "one_cmpldi2"
 ;;   [(set (match_operand:DI 0 "register_operand" "=r")
 ;; 	(not:DI (match_operand:DI 1 "register_operand" "r")))]
diff --git a/gcc/config/frv/predicates.md b/gcc/config/frv/predicates.md
index 4c32120237e..a1eaf9a799a 100644
--- a/gcc/config/frv/predicates.md
+++ b/gcc/config/frv/predicates.md
@@ -105,7 +105,7 @@
   return FALSE;
 })
 
-;; Return 1 if operand is a GPR register or 12 bit signed immediate.
+;; Return 1 if operand is a GPR register or 12-bit signed immediate.
 
 (define_predicate "gpr_or_int12_operand"
   (match_code "reg,subreg,const_int,const")
@@ -165,7 +165,7 @@
   return FALSE;
 })
 
-;; Return 1 if operand is a register or 10 bit signed immediate.
+;; Return 1 if operand is a register or 10-bit signed immediate.
 
 (define_predicate "gpr_or_int10_operand"
   (match_code "reg,subreg,const_int")
@@ -486,7 +486,7 @@
 	  || frv_legitimate_memory_operand (op, mode, FALSE));
 })
 
-;; Return 1 if operand is a 12 bit signed immediate.
+;; Return 1 if operand is a 12-bit signed immediate.
 
 (define_predicate "int12_operand"
   (match_code "const_int")
@@ -1110,7 +1110,7 @@
   return ((INTVAL (op) & 0xffff) == 0);
 })
 
-;; Return 1 if operand is a 16 bit unsigned immediate.
+;; Return 1 if operand is a 16-bit unsigned immediate.
 
 (define_predicate "uint16_operand"
   (match_code "const_int")
@@ -1445,7 +1445,7 @@
     }
 })
 
-;; Return 1 if operand is a register or 6 bit signed immediate.
+;; Return 1 if operand is a register or 6-bit signed immediate.
 
 (define_predicate "fpr_or_int6_operand"
   (match_code "reg,subreg,const_int")
@@ -1470,7 +1470,7 @@
   return FPR_OR_PSEUDO_P (REGNO (op));
 })
 
-;; Return 1 if operand is a 6 bit signed immediate.
+;; Return 1 if operand is a 6-bit signed immediate.
 
 (define_predicate "int6_operand"
   (match_code "const_int")
@@ -1481,7 +1481,7 @@
   return IN_RANGE_P (INTVAL (op), -32, 31);
 })
 
-;; Return 1 if operand is a 5 bit signed immediate.
+;; Return 1 if operand is a 5-bit signed immediate.
 
 (define_predicate "int5_operand"
   (match_code "const_int")
@@ -1489,7 +1489,7 @@
   return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
 })
 
-;; Return 1 if operand is a 5 bit unsigned immediate.
+;; Return 1 if operand is a 5-bit unsigned immediate.
 
 (define_predicate "uint5_operand"
   (match_code "const_int")
@@ -1497,7 +1497,7 @@
   return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
 })
 
-;; Return 1 if operand is a 4 bit unsigned immediate.
+;; Return 1 if operand is a 4-bit unsigned immediate.
 
 (define_predicate "uint4_operand"
   (match_code "const_int")
@@ -1505,7 +1505,7 @@
   return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
 })
 
-;; Return 1 if operand is a 1 bit unsigned immediate (0 or 1).
+;; Return 1 if operand is a 1-bit unsigned immediate (0 or 1).
 
 (define_predicate "uint1_operand"
   (match_code "const_int")