* config/frv/frv.c, config/frv/frv.h, config/frv/frv.md,

	config/frv/predicates.md: Follow spelling conventions.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@122118 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 22 insertions, 22 deletions

diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md
index d393204216b..14c863f3c49 100644
--- a/gcc/config/frv/frv.md
+++ b/gcc/config/frv/frv.md
@@ -133,11 +133,11 @@
 ;;     than a word wide.  Constraints for these operands should use `n' rather
 ;;     than `i'.
 ;;
-;; 'I' First machine-dependent integer constant (6 bit signed ints).
-;; 'J' Second machine-dependent integer constant (10 bit signed ints).
+;; 'I' First machine-dependent integer constant (6-bit signed ints).
+;; 'J' Second machine-dependent integer constant (10-bit signed ints).
 ;; 'K' Third machine-dependent integer constant (-2048).
-;; 'L' Fourth machine-dependent integer constant (16 bit signed ints).
-;; 'M' Fifth machine-dependent integer constant (16 bit unsigned ints).
+;; 'L' Fourth machine-dependent integer constant (16-bit signed ints).
+;; 'M' Fifth machine-dependent integer constant (16-bit unsigned ints).
 ;; 'N' Sixth machine-dependent integer constant (-2047..-1).
 ;; 'O' Seventh machine-dependent integer constant (zero).
 ;; 'P' Eighth machine-dependent integer constant (1..2047).
@@ -2916,7 +2916,7 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 32 bit Integer arithmetic
+;; :: 32-bit Integer arithmetic
 ;; ::
 ;; ::::::::::::::::::::
 
@@ -2943,7 +2943,7 @@
   [(set_attr "length" "4")
    (set_attr "type" "int")])
 
-;; Signed multiplication producing 64 bit results from 32 bit inputs
+;; Signed multiplication producing 64-bit results from 32-bit inputs
 ;; Note, frv doesn't have a 32x32->32 bit multiply, but the compiler
 ;; will do the 32x32->64 bit multiply and use the bottom word.
 (define_expand "mulsidi3"
@@ -2978,7 +2978,7 @@
   [(set_attr "length" "4")
    (set_attr "type" "mul")])
 
-;; Unsigned multiplication producing 64 bit results from 32 bit inputs
+;; Unsigned multiplication producing 64-bit results from 32-bit inputs
 (define_expand "umulsidi3"
   [(set (match_operand:DI 0 "even_gpr_operand" "")
 	(mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" ""))
@@ -3051,7 +3051,7 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 64 bit Integer arithmetic
+;; :: 64-bit Integer arithmetic
 ;; ::
 ;; ::::::::::::::::::::
 
@@ -3230,7 +3230,7 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 32 bit floating point arithmetic
+;; :: 32-bit floating point arithmetic
 ;; ::
 ;; ::::::::::::::::::::
 
@@ -3325,7 +3325,7 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 64 bit floating point arithmetic
+;; :: 64-bit floating point arithmetic
 ;; ::
 ;; ::::::::::::::::::::
 
@@ -3420,7 +3420,7 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 32 bit Integer Shifts and Rotates
+;; :: 32-bit Integer Shifts and Rotates
 ;; ::
 ;; ::::::::::::::::::::
 
@@ -3475,7 +3475,7 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 64 bit Integer Shifts and Rotates
+;; :: 64-bit Integer Shifts and Rotates
 ;; ::
 ;; ::::::::::::::::::::
 
@@ -3527,11 +3527,11 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 32 Bit Integer Logical operations
+;; :: 32-Bit Integer Logical operations
 ;; ::
 ;; ::::::::::::::::::::
 
-;; Logical AND, 32 bit integers
+;; Logical AND, 32-bit integers
 (define_insn "andsi3_media"
   [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
 	(and:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
@@ -3559,7 +3559,7 @@
   ""
   "")
 
-;; Inclusive OR, 32 bit integers
+;; Inclusive OR, 32-bit integers
 (define_insn "iorsi3_media"
   [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
 	(ior:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
@@ -3587,7 +3587,7 @@
   ""
   "")
 
-;; Exclusive OR, 32 bit integers
+;; Exclusive OR, 32-bit integers
 (define_insn "xorsi3_media"
   [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
 	(xor:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
@@ -3615,7 +3615,7 @@
   ""
   "")
 
-;; One's complement, 32 bit integers
+;; One's complement, 32-bit integers
 (define_insn "one_cmplsi2_media"
   [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
 	(not:SI (match_operand:SI 1 "gpr_or_fpr_operand" "d,f")))]
@@ -3643,11 +3643,11 @@
 
 ;; ::::::::::::::::::::
 ;; ::
-;; :: 64 Bit Integer Logical operations
+;; :: 64-Bit Integer Logical operations
 ;; ::
 ;; ::::::::::::::::::::
 
-;; Logical AND, 64 bit integers
+;; Logical AND, 64-bit integers
 ;; (define_insn "anddi3"
 ;;   [(set (match_operand:DI 0 "register_operand" "=r")
 ;; 	(and:DI (match_operand:DI 1 "register_operand" "%r")
@@ -3656,7 +3656,7 @@
 ;;   "anddi3 %0,%1,%2"
 ;;   [(set_attr "length" "4")])
 
-;; Inclusive OR, 64 bit integers
+;; Inclusive OR, 64-bit integers
 ;; (define_insn "iordi3"
 ;;   [(set (match_operand:DI 0 "register_operand" "=r")
 ;; 	(ior:DI (match_operand:DI 1 "register_operand" "%r")
@@ -3665,7 +3665,7 @@
 ;;   "iordi3 %0,%1,%2"
 ;;   [(set_attr "length" "4")])
 
-;; Exclusive OR, 64 bit integers
+;; Exclusive OR, 64-bit integers
 ;; (define_insn "xordi3"
 ;;   [(set (match_operand:DI 0 "register_operand" "=r")
 ;; 	(xor:DI (match_operand:DI 1 "register_operand" "%r")
@@ -3674,7 +3674,7 @@
 ;;   "xordi3 %0,%1,%2"
 ;;   [(set_attr "length" "4")])
 
-;; One's complement, 64 bit integers
+;; One's complement, 64-bit integers
 ;; (define_insn "one_cmpldi2"
 ;;   [(set (match_operand:DI 0 "register_operand" "=r")
 ;; 	(not:DI (match_operand:DI 1 "register_operand" "r")))]