* config/frv/frv.c (frv_legitimize_tls_address): New.

	(TARGET_HAVE_TLS): Define.
	(FRV_SYMBOL_REF_TLS_P): Define.
	(frv_override_options): Handle new register classes.
	(frv_legitimate_address_p): Reject tls addresses.
	(frv_legitimize_address): Handle TLS addresses.
	(gen_inlined_tls_plt): New.
	(gen_tlsmoff): New.
	(frv_legitimize_tls_address): New.
	(unspec_got_name): Add TLS entries.
	(got12_operand): Add R_FRV_TLSMOFF12 case.
	(frv_emit_move): Fixup TLS addresses.
	(frv_emit_movsi): Legitimize TLS addresses.

	* config/frv/frv.h (MASK_BIG_TLS): New.
	(TARGET_BIG_TLS): New.
	(HAVE_AS_TLS): Define.
	(TARGET_SWITCHES): Add -mTLS and -mtls options.
	(enum reg_class): Add GR8_REGS, GR9_REGS, GR89_REGS.
	(REG_CLASS_NAMES): Same.
	(REG_CLASS_CONTENTS): Same.
	(CONSTRAINT_LEN): New.
	(REG_CLASS_FROM_CONSTRAINT): New.
	(PREDICATE_CODES): Add symbolic_operand.

	* config/frv/frv.md (define_constants): Add UNSPEC_GETTLSOFF,
	UNSPEC_TLS_LOAD_GOTTLSOFF12, UNSPEC_TLS_INDIRECT_CALL,
	UNSPEC_TLS_TLSDESC_LDD, UNSPEC_TLS_TLSDESC_LDD_AUX,
	UNSPEC_TLS_TLSOFF_LD, UNSPEC_TLS_LDDI, UNSPEC_TLSOFF_HILO,
	R_FRV_GOTTLSOFF_HI, R_FRV_GOTTLSOFF_LO, R_FRV_TLSMOFFHI,
	R_FRV_TLSMOFFLO, R_FRV_TLSMOFF12, R_FRV_TLSDESCHI,
	R_FRV_TLSDESCLO, R_FRV_GOTTLSDESCHI, R_FRV_GOTTLSDESCLO, GR8_REG,
	GR9_REG, GR14_REG, LRREG.
	(type): Add load_or_call attribute.
	("load_or_call"): New reservation.
	("call_gettlsoff"): New.
	("tls_indirect_call"): New.
	("tls_load_gottlsoff12"): New.
	("tlsoff_hilo"): New.
	("tls_tlsdesc_ldd"): New.
	("tls_tlsoff_ld"): New.
	("tls_lddi"): New.

	* config/frv/frv-protos.h (symbolic_operand): Protoize.

        * config/frv/frv.h (ASM_OUTPUT_DWARF_DTPREL): Define.
        * config/frv/frv-protos.h (frv_output_dwarf_dtprel): Declare.
        * config/frv/frv.c (TLS_BIAS): Define.
        (frv_output_dwarf_dtprel): New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@94237 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 131 insertions, 3 deletions

diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md
index 269de036fef..bab77557273 100644
--- a/gcc/config/frv/frv.md
+++ b/gcc/config/frv/frv.md
@@ -1,5 +1,6 @@
 ;; Frv Machine Description
-;; Copyright (C) 1999, 2000, 2001, 2003, 2004 Free Software Foundation, Inc.
+;; Copyright (C) 1999, 2000, 2001, 2003, 2004, 2005 Free Software Foundation,
+;; Inc.
 ;; Contributed by Red Hat, Inc.
 
 ;; This file is part of GCC.
@@ -41,6 +42,15 @@
    (UNSPEC_GOT			7)
    (UNSPEC_LDD			8)
 
+   (UNSPEC_GETTLSOFF			200)
+   (UNSPEC_TLS_LOAD_GOTTLSOFF12		201)
+   (UNSPEC_TLS_INDIRECT_CALL		202)
+   (UNSPEC_TLS_TLSDESC_LDD		203)
+   (UNSPEC_TLS_TLSDESC_LDD_AUX		204)
+   (UNSPEC_TLS_TLSOFF_LD		205)
+   (UNSPEC_TLS_LDDI			206)
+   (UNSPEC_TLSOFF_HILO			207)
+
    (R_FRV_GOT12			11)
    (R_FRV_GOTHI			12)
    (R_FRV_GOTLO			13)
@@ -58,7 +68,21 @@
    (R_FRV_GPREL12		25)
    (R_FRV_GPRELHI		26)
    (R_FRV_GPRELLO		27)
-
+   (R_FRV_GOTTLSOFF_HI		28)
+   (R_FRV_GOTTLSOFF_LO		29)
+   (R_FRV_TLSMOFFHI		30)
+   (R_FRV_TLSMOFFLO           	31)
+   (R_FRV_TLSMOFF12           	32)
+   (R_FRV_TLSDESCHI           	33)
+   (R_FRV_TLSDESCLO           	34)
+   (R_FRV_GOTTLSDESCHI		35)
+   (R_FRV_GOTTLSDESCLO		36)
+
+   (GR8_REG			8)
+   (GR9_REG			9)
+   (GR14_REG			14)
+   ;; LR_REG conflicts with definition in frv.h
+   (LRREG                       169)
    (FDPIC_REG			15)
    ])
 
@@ -330,7 +354,7 @@
 ;; Instruction type
 ;; "unknown" must come last.
 (define_attr "type"
-  "int,sethi,setlo,mul,div,gload,gstore,fload,fstore,movfg,movgf,macc,scan,cut,branch,jump,jumpl,call,spr,trap,fnop,fsconv,fsadd,fscmp,fsmul,fsmadd,fsdiv,sqrt_single,fdconv,fdadd,fdcmp,fdmul,fdmadd,fddiv,sqrt_double,mnop,mlogic,maveh,msath,maddh,mqaddh,mpackh,munpackh,mdpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx,mcut,mclracc,mclracca,mdunpackh,mbhconve,mrdacc,mwtacc,maddacc,mdaddacc,mabsh,mdrot,mcpl,mdcut,mqsath,mqlimh,mqshift,mset,ccr,multi,unknown"
+  "int,sethi,setlo,mul,div,gload,gstore,fload,fstore,movfg,movgf,macc,scan,cut,branch,jump,jumpl,call,spr,trap,fnop,fsconv,fsadd,fscmp,fsmul,fsmadd,fsdiv,sqrt_single,fdconv,fdadd,fdcmp,fdmul,fdmadd,fddiv,sqrt_double,mnop,mlogic,maveh,msath,maddh,mqaddh,mpackh,munpackh,mdpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx,mcut,mclracc,mclracca,mdunpackh,mbhconve,mrdacc,mwtacc,maddacc,mdaddacc,mabsh,mdrot,mcpl,mdcut,mqsath,mqlimh,mqshift,mset,ccr,multi,load_or_call,unknown"
   (const_string "unknown"))
 
 (define_attr "acc_group" "none,even,odd"
@@ -529,6 +553,11 @@
   (eq_attr "type" "trap,spr,unknown,multi")
   "c + control")
 
+;; Reservation for relaxable calls to gettlsoff.
+(define_insn_reservation "load_or_call" 3
+  (eq_attr "type" "load_or_call")
+  "c + control")
+
 ;; ::::::::::::::::::::
 ;; ::
 ;; :: Generic/FR500 scheduler description
@@ -8134,3 +8163,102 @@
   "TARGET_FR500_FR550_BUILTINS"
   "nop.p\\n\\tnldub @(%0, gr0), gr0"
   [(set_attr "length" "8")])
+
+;; TLS patterns
+
+(define_insn "call_gettlsoff"
+  [(set (match_operand:SI 0 "register_operand" "=D09")
+	(unspec:SI
+	 [(match_operand:SI 1 "symbolic_operand" "")]
+	 UNSPEC_GETTLSOFF))
+   (clobber (reg:SI GR8_REG))
+   (clobber (reg:SI LRREG))
+   (use (match_operand:SI 2 "register_operand" "D15"))]
+  "HAVE_AS_TLS"
+  "call #gettlsoff(%a1)"
+  [(set_attr "length" "4")
+   (set_attr "type" "load_or_call")])
+
+;; Reads GR8 and GR9.
+;; Clobbers GR8.
+;; Modifies GR9.
+(define_insn "tls_indirect_call"
+  [(set (match_operand:SI 0 "register_operand" "=D09")
+	(unspec:SI
+	 [(match_operand:SI 1 "symbolic_operand" "")
+	  (match_operand:DI 2 "register_operand" "D89")]
+	 UNSPEC_TLS_INDIRECT_CALL))
+   (clobber (match_operand:SI 3 "register_operand" "=D08"))
+   (clobber (reg:SI LRREG))
+   ;; If there was a way to represent the fact that we don't need GR9
+   ;; or GR15 to be set before this instruction (it could be in
+   ;; parallel), we could use it here.  This change wouldn't apply to
+   ;; call_gettlsoff, thought, since the linker may turn the latter
+   ;; into ldi @(gr15,offset),gr9.
+   (use (match_operand:SI 4 "register_operand" "D15"))]
+  "HAVE_AS_TLS"
+  "calll #gettlsoff(%a1)@(%2,gr0)"
+  [(set_attr "length" "4")
+   (set_attr "type" "jumpl")])
+
+(define_insn "tls_load_gottlsoff12"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(unspec:SI
+	 [(match_operand:SI 1 "symbolic_operand" "")
+	  (match_operand:SI 2 "register_operand" "r")]
+	 UNSPEC_TLS_LOAD_GOTTLSOFF12))]
+  "HAVE_AS_TLS"
+  "ldi @(%2, #gottlsoff12(%1)), %0"
+  [(set_attr "length" "4")])
+
+(define_expand "tlsoff_hilo"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(high:SI (const:SI (unspec:SI
+			    [(match_operand:SI 1 "symbolic_operand" "")
+			     (match_operand:SI 2 "immediate_operand" "n")]
+			    UNSPEC_GOT))))
+   (set (match_dup 0)
+	(lo_sum:SI (match_dup 0)
+		   (const:SI (unspec:SI [(match_dup 1)
+					 (match_dup 3)] UNSPEC_GOT))))]
+  ""
+  "
+{
+  operands[3] = GEN_INT (INTVAL (operands[2]) + 1);
+}")
+
+;; Just like movdi_ldd, but with relaxation annotations.
+(define_insn "tls_tlsdesc_ldd"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec:DI [(mem:DI (unspec:SI
+			     [(match_operand:SI 1 "register_operand" "r")
+			      (match_operand:SI 2 "register_operand" "r")
+			      (match_operand:SI 3 "symbolic_operand" "")]
+			     UNSPEC_TLS_TLSDESC_LDD_AUX))]
+		   UNSPEC_TLS_TLSDESC_LDD))]
+  ""
+  "ldd #tlsdesc(%a3)@(%1,%2), %0"
+  [(set_attr "length" "4")
+   (set_attr "type" "gload")])
+
+(define_insn "tls_tlsoff_ld"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(mem:SI (unspec:SI
+		 [(match_operand:SI 1 "register_operand" "r")
+		  (match_operand:SI 2 "register_operand" "r")
+		  (match_operand:SI 3 "symbolic_operand" "")]
+		 UNSPEC_TLS_TLSOFF_LD)))]
+  ""
+  "ld #tlsoff(%a3)@(%1,%2), %0"
+  [(set_attr "length" "4")
+   (set_attr "type" "gload")])
+
+(define_insn "tls_lddi"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec:DI [(match_operand:SI 1 "symbolic_operand" "")
+		    (match_operand:SI 2 "register_operand" "d")]
+		   UNSPEC_TLS_LDDI))]
+  ""
+  "lddi @(%2, #gottlsdesc12(%a1)), %0"
+  [(set_attr "length" "4")
+   (set_attr "type" "gload")])