diff options
| author | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-10-15 06:38:02 +0000 |
|---|---|---|
| committer | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-10-15 06:38:02 +0000 |
| commit | 262115d1dbd1098839d54bf08c5c89f42a248ebc (patch) | |
| tree | 6961d842b244b73c4676dcdd51ab81f9796bfce8 /gcc/config/fr30 | |
| parent | f5fddbf2d840fc50ed043ec01cd90a2bf489d23b (diff) | |
| download | gcc-262115d1dbd1098839d54bf08c5c89f42a248ebc.tar.gz | |
* 1750a.md (movstrqi): Add missing output reload constraint.
(call_value): Likewise.
* a29k.md (cpxxx patterns): Add missing match_operator mode.
(jmpfdec): Add missing inout reload constraint.
* elxsi.md (addsi patterns): Add missing output reload constraint.
(move from sp): Use @ alternates.
(call_value): No constraint on output.
* fr30.md (movsi_pop): Add missing output reload constraint.
(movsf_constant_store): Likewise.
(splits): Remove constraints.
(subsi3): Add missing mode.
* i370.md (cmpstrsi+1): Add missing output reload constraint.
(call_value): Likewise.
* i960.md (cmpinc/cmpdec patterns): Add inout reload constraints.
* m32r.h (PREDICATE_CODES): Add seth_add3_operand.
* m32r.md (movsicc_internal): Add output reload constraint.
(movstrsi_internal): Add inout reload constraints.
* m88k.h (reg_names): Don't declare.
(SPECIAL_MODE_PREDICATES): New.
* m88k.md (*): Use register_operand not reg_or_0_operand
on destinations.
* mn10200.h (PREDICATE_CODES): New.
* ns32k.md (ffs pattern): Add output reload constraint.
* pdp11.md (sob pattern): Add inout reload constraint.
* sh.md (splits): Remove constraints.
(indirect_jump_scratch, fpu_switch): Add output reload constraint.
* v850.md (pattern_is_ok_for_epilogue): Likewise.
* vax.md (jgequ pattern): Add inout reload constraint.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@30008 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/fr30')
| -rw-r--r-- | gcc/config/fr30/fr30.md | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md index f0ac26a2374..6618fe3a203 100644 --- a/gcc/config/fr30/fr30.md +++ b/gcc/config/fr30/fr30.md @@ -149,7 +149,7 @@ ;; Pop a register off the stack (define_insn "movsi_pop" - [(set:SI (match_operand:SI 0 "register_operand" "a") + [(set:SI (match_operand:SI 0 "register_operand" "=a") (mem:SI (post_inc:SI (reg:SI 15))))] "" "ld @r15+, %0" @@ -288,8 +288,8 @@ ;; If we are loading a small negative constant we can save space ;; and time by loading the positive value and then sign extending it. (define_split - [(set (match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "immediate_operand" "i"))] + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "immediate_operand" ""))] "INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128" [(set:SI (match_dup 0) (match_dup 2)) (set:SI (match_dup 0) (sign_extend:SI (subreg:QI (match_dup 0) 0)))] @@ -302,8 +302,8 @@ ;; not have any of its bottom 24 bit set, then we can save time ;; and space by loading the byte value and shifting it into place. (define_split - [(set (match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "immediate_operand" "i"))] + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "immediate_operand" ""))] "(INTVAL (operands[1]) < 0) && (INTVAL (operands[1]) & 0x00ffffff == 0)" [(set:SI (match_dup 0) (match_dup 2)) (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (const_int 24))) @@ -319,8 +319,8 @@ ;; range, then we can save time and space by loading the byte value ;; and shifting it into place. (define_split - [(set (match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "immediate_operand" "i"))] + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "immediate_operand" ""))] "(INTVAL (operands[1]) > 0x00ffffff) && ((INTVAL (operands[1]) >> exact_log2 (INTVAL (operands[1]) & (- INTVAL (operands[1])))) < 0x100)" [(set:SI (match_dup 0) (match_dup 2)) @@ -528,7 +528,7 @@ ) (define_insn "*movsf_constant_store" - [(set (match_operand:SF 0 "memory_operand" "m") + [(set (match_operand:SF 0 "memory_operand" "=m") (match_operand:SF 1 "immediate_operand" "F"))] "" "* @@ -695,8 +695,8 @@ (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=r") - (minus (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "register_operand" "r")))] + (minus:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "register_operand" "r")))] "" "subn %2, %0" ) |