* config/vxlib.c: Fix comment typos.

	* config/alpha/alpha.c: Likewise.
	* config/arm/arm.c: Likewise.
	* config/arm/arm.md: Likewise.
	* config/c4x/c4x.c: Likewise.
	* config/c4x/c4x.md: Likewise.
	* config/cris/cris.h: Likewise.
	* config/cris/cris.md: Likewise.
	* config/fr30/fr30.c: Likewise.
	* config/fr30/fr30.h: Likewise.
	* config/fr30/fr30.md: Likewise.
	* config/frv/frv.c: Likewise.
	* config/frv/frv.md: Likewise.
	* config/frv/frvbegin.c: Likewise.
	* config/i386/athlon.md: Likewise.
	* config/i386/i386.c: Likewise.
	* config/i386/i386.md: Likewise.
	* config/i386/sco5.h: Likewise.
	* config/ia64/ia64.md: Likewise.
	* config/ip2k/ip2k.c: Likewise.
	* config/ip2k/ip2k.md: Likewise.
	* config/m68hc11/m68hc11.h: Likewise.
	* config/m68k/m68k.h: Likewise.
	* config/mips/mips.c: Likewise.
	* config/rs6000/rs6000.c: Likewise.
	* config/s390/s390.md: Likewise.
	* config/sh/sh.h: Likewise.
	* config/sparc/sparc.md: Likewise.
	* config/v850/v850.c: Likewise.
	* config/v850/v850.h: Likewise.
	* config/v850/v850.md: Likewise.
	* config/xtensa/xtensa.c: Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@74596 138bc75d-0d04-0410-961f-82ee72b054a4

2 files changed, 5 insertions, 5 deletions

diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h
index 9f130d6448c..69483fae1fd 100644
--- a/gcc/config/cris/cris.h
+++ b/gcc/config/cris/cris.h
@@ -259,7 +259,7 @@ extern const char *cris_elinux_stacksize_str;
 /* This needs to be at least 32 bits.  */
 extern int target_flags;
 
-/* Currently this just affects aligment.  FIXME:  Redundant with
+/* Currently this just affects alignment.  FIXME:  Redundant with
    TARGET_ALIGN_BY_32, or put machine stuff here?  */
 #define TARGET_MASK_SVINTO 1
 #define TARGET_SVINTO (target_flags & TARGET_MASK_SVINTO)
@@ -850,7 +850,7 @@ enum reg_class {NO_REGS, ALL_REGS, LIM_REG_CLASSES};
 
 /* If we would ever need an exact mapping between canonical register
    number and dwarf frame register, we would either need to include all
-   registers in the gcc decription (with some marked fixed of course), or
+   registers in the gcc description (with some marked fixed of course), or
    an inverse mapping from dwarf register to gcc register.  There is one
    need in dwarf2out.c:expand_builtin_init_dwarf_reg_sizes.  Right now, I
    don't see that we need exact correspondence between DWARF *frame*
diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md
index ea347fd74fa..8fb07039f04 100644
--- a/gcc/config/cris/cris.md
+++ b/gcc/config/cris/cris.md
@@ -31,7 +31,7 @@
 ;; There are several instructions that are orthogonal in size, and seems
 ;; they could be matched by a single pattern without a specified size
 ;; for the operand that is orthogonal.  However, this did not work on
-;; gcc-2.7.2 (and problably not on gcc-2.8.1), relating to that when a
+;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a
 ;; constant is substituted into an operand, the actual mode must be
 ;; deduced from the pattern.  There is reasonable hope that that has been
 ;; fixed, so FIXME: try again.
@@ -77,7 +77,7 @@
 ;; The possible values are "yes", "no" and "has_slot".  Yes/no means if
 ;; the insn is slottable or not.  Has_slot means that the insn is a
 ;; return insn or branch insn (which are not considered slottable since
-;; that is generally true).  Having the semmingly illogical value
+;; that is generally true).  Having the seemingly illogical value
 ;; "has_slot" means we do not have to add another attribute just to say
 ;; that an insn has a delay-slot, since it also infers that it is not
 ;; slottable.  Better names for the attribute were found to be longer and
@@ -1354,7 +1354,7 @@
   "movs.b %1,%0"
   [(set_attr "slottable" "yes,yes,no")])
 
-;; To do a byte->word exension, extend to dword, exept that the top half
+;; To do a byte->word extension, extend to dword, exept that the top half
 ;; of the register will be clobbered.  FIXME: Perhaps this is not needed.
 
 (define_insn "extendqihi2"