diff options
| author | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-09-09 11:25:12 +0000 |
|---|---|---|
| committer | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-09-09 11:25:12 +0000 |
| commit | 63b74b739ed97f3d276fa2f55488ce184252c166 (patch) | |
| tree | 7238d4fa46495075e4808375c9d4cccf40bcdf26 /gcc/config/arm | |
| parent | bd23734550a2518b66f54a3bd69db6c982b6a590 (diff) | |
| download | gcc-63b74b739ed97f3d276fa2f55488ce184252c166.tar.gz | |
[ARM][4/7] Convert FP mnemonics to UAL | vcvt patterns
* config/arm/vfp.md (*extendsfdf2_vfp): Use UAL assembly syntax.
(*truncdfsf2_vfp): Likewise.
(*truncsisf2_vfp): Likewise.
(*truncsidf2_vfp): Likewise.
(fixuns_truncsfsi2): Likewise.
(fixuns_truncdfsi2): Likewise.
(*floatsisf2_vfp): Likewise.
(*floatsidf2_vfp): Likewise.
(floatunssisf2): Likewise.
(floatunssidf2): Likewise.
* gcc.target/arm/vfp-1.c: Updated expected assembly.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215053 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/arm')
| -rw-r--r-- | gcc/config/arm/vfp.md | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index d165d7cf968..0afd8bf060b 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -953,7 +953,7 @@ [(set (match_operand:DF 0 "s_register_operand" "=w") (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "fcvtds%?\\t%P0, %1" + "vcvt%?.f64.f32\\t%P0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] @@ -963,7 +963,7 @@ [(set (match_operand:SF 0 "s_register_operand" "=t") (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "fcvtsd%?\\t%0, %P1" + "vcvt%?.f32.f64\\t%0, %P1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] @@ -993,7 +993,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=t") (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" - "ftosizs%?\\t%0, %1" + "vcvt%?.s32.f32\\t%0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvtf2i")] @@ -1003,7 +1003,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=t") (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "ftosizd%?\\t%0, %P1" + "vcvt%?.s32.f64\\t%0, %P1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvtf2i")] @@ -1014,7 +1014,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=t") (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" - "ftouizs%?\\t%0, %1" + "vcvt%?.u32.f32\\t%0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvtf2i")] @@ -1024,7 +1024,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=t") (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "ftouizd%?\\t%0, %P1" + "vcvt%?.u32.f64\\t%0, %P1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvtf2i")] @@ -1035,7 +1035,7 @@ [(set (match_operand:SF 0 "s_register_operand" "=t") (float:SF (match_operand:SI 1 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" - "fsitos%?\\t%0, %1" + "vcvt%?.f32.s32\\t%0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvti2f")] @@ -1045,7 +1045,7 @@ [(set (match_operand:DF 0 "s_register_operand" "=w") (float:DF (match_operand:SI 1 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "fsitod%?\\t%P0, %1" + "vcvt%?.f64.s32\\t%P0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvti2f")] @@ -1056,7 +1056,7 @@ [(set (match_operand:SF 0 "s_register_operand" "=t") (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" - "fuitos%?\\t%0, %1" + "vcvt%?.f32.u32\\t%0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvti2f")] @@ -1066,7 +1066,7 @@ [(set (match_operand:DF 0 "s_register_operand" "=w") (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "fuitod%?\\t%P0, %1" + "vcvt%?.f64.u32\\t%P0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvti2f")] |