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| author | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-06-01 10:44:07 +0000 |
|---|---|---|
| committer | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-06-01 10:44:07 +0000 |
| commit | ff1c72999d6e4d7393324a5e726d596c6f71a36d (patch) | |
| tree | c123705aabb7badac4b55d231fda239130b1c9da /gcc/config/arm | |
| parent | c17f4a5a2eb72929724bc3450567cb18c0c878f7 (diff) | |
| download | gcc-ff1c72999d6e4d7393324a5e726d596c6f71a36d.tar.gz | |
[ARM] Use proper output modifier for DImode register in store exclusive patterns
* config/arm/sync.md (arm_store_exclusive<mode>):
Use 'H' output modifier on operands[2] rather than creating a new
entry in out-of-bounds memory of the operands array.
(arm_store_release_exclusivedi): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@236984 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/arm')
| -rw-r--r-- | gcc/config/arm/sync.md | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 0589e4d8905..abcfbcb1eac 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -452,14 +452,13 @@ { if (<MODE>mode == DImode) { - rtx value = operands[2]; /* The restrictions on target registers in ARM mode are that the two registers are consecutive and the first one is even; Thumb is actually more flexible, but DI should give us this anyway. - Note that the 1st register always gets the lowest word in memory. */ - gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2); - operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1); - return "strexd%?\t%0, %2, %3, %C1"; + Note that the 1st register always gets the + lowest word in memory. */ + gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2); + return "strexd%?\t%0, %2, %H2, %C1"; } return "strex<sync_sfx>%?\t%0, %2, %C1"; } @@ -475,11 +474,9 @@ VUNSPEC_SLX))] "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN" { - rtx value = operands[2]; /* See comment in arm_store_exclusive<mode> above. */ - gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2); - operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1); - return "stlexd%?\t%0, %2, %3, %C1"; + gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2); + return "stlexd%?\t%0, %2, %H2, %C1"; } [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) |