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| author | Christophe Lyon <christophe.lyon@linaro.org> | 2012-09-13 08:55:30 +0000 |
|---|---|---|
| committer | Christophe Lyon <clyon@gcc.gnu.org> | 2012-09-13 10:55:30 +0200 |
| commit | e619b1739d00d5408eedc7b7a04c59de2aabf39e (patch) | |
| tree | e9f29450bb47b95908b27391843f15007f6200e7 /gcc/config/arm | |
| parent | b9e75f4fccc492cdfd5e5498cb92a23f3b7a25b5 (diff) | |
| download | gcc-e619b1739d00d5408eedc7b7a04c59de2aabf39e.tar.gz | |
arm.md (arm_rev): Factorize thumb1, thumb2 and arm variants for rev instruction..
2012-09-13 Christophe Lyon <christophe.lyon@linaro.org>
Richard Earnshaw <rearnsha@arm.com>
gcc/
* config/arm/arm.md (arm_rev): Factorize thumb1, thumb2 and arm
variants for rev instruction..
(thumb1_rev): Delete pattern.
(arm_revsh): New pattern to support builtin_bswap16.
(arm_rev16, bswaphi2): Likewise.
gcc/testsuite/
* gcc.target/arm/builtin-bswap-1.c: New testcase.
Co-Authored-By: Richard Earnshaw <rearnsha@arm.com>
From-SVN: r191243
Diffstat (limited to 'gcc/config/arm')
| -rw-r--r-- | gcc/config/arm/arm.md | 57 |
1 files changed, 43 insertions, 14 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index a60e659bf68..43a9f1fef3f 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -11371,20 +11371,15 @@ ) (define_insn "*arm_rev" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_32BIT && arm_arch6" - "rev%?\t%0, %1" - [(set_attr "predicable" "yes") - (set_attr "length" "4")] -) - -(define_insn "*thumb1_rev" - [(set (match_operand:SI 0 "s_register_operand" "=l") - (bswap:SI (match_operand:SI 1 "s_register_operand" "l")))] - "TARGET_THUMB1 && arm_arch6" - "rev\t%0, %1" - [(set_attr "length" "2")] + [(set (match_operand:SI 0 "s_register_operand" "=l,l,r") + (bswap:SI (match_operand:SI 1 "s_register_operand" "l,l,r")))] + "arm_arch6" + "@ + rev\t%0, %1 + rev%?\t%0, %1 + rev%?\t%0, %1" + [(set_attr "arch" "t1,t2,32") + (set_attr "length" "2,2,4")] ) (define_expand "arm_legacy_rev" @@ -11472,6 +11467,40 @@ " ) +;; bswap16 patterns: use revsh and rev16 instructions for the signed +;; and unsigned variants, respectively. For rev16, expose +;; byte-swapping in the lower 16 bits only. +(define_insn "*arm_revsh" + [(set (match_operand:SI 0 "s_register_operand" "=l,l,r") + (sign_extend:SI (bswap:HI (match_operand:HI 1 "s_register_operand" "l,l,r"))))] + "arm_arch6" + "@ + revsh\t%0, %1 + revsh%?\t%0, %1 + revsh%?\t%0, %1" + [(set_attr "arch" "t1,t2,32") + (set_attr "length" "2,2,4")] +) + +(define_insn "*arm_rev16" + [(set (match_operand:HI 0 "s_register_operand" "=l,l,r") + (bswap:HI (match_operand:HI 1 "s_register_operand" "l,l,r")))] + "arm_arch6" + "@ + rev16\t%0, %1 + rev16%?\t%0, %1 + rev16%?\t%0, %1" + [(set_attr "arch" "t1,t2,32") + (set_attr "length" "2,2,4")] +) + +(define_expand "bswaphi2" + [(set (match_operand:HI 0 "s_register_operand" "=r") + (bswap:HI (match_operand:HI 1 "s_register_operand" "r")))] +"arm_arch6" +"" +) + ;; Load the load/store multiple patterns (include "ldmstm.md") |