diff options
| author | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-04-15 10:43:43 +0000 |
|---|---|---|
| committer | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-04-15 10:43:43 +0000 |
| commit | f6bbdcf62628538af217e1dfbc1d1c373af629fe (patch) | |
| tree | 5d5c0f95ead98d820847ebc2339f133fefbd14ab /gcc/config/arm/predicates.md | |
| parent | 8aaed91dfc5f8fcd17fd6b61de3a6d68e59b5e1e (diff) | |
| download | gcc-f6bbdcf62628538af217e1dfbc1d1c373af629fe.tar.gz | |
2013-04-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (const_ok_for_dimode_op): Handle AND case.
* config/arm/arm.md (*anddi3_insn): Change to insn_and_split.
* config/arm/constraints.md (De): New constraint.
* config/arm/neon.md (anddi3_neon): Delete.
(neon_vand<mode>): Expand to standard anddi3 pattern.
* config/arm/predicates.md (imm_for_neon_inv_logic_operand):
Move earlier in the file.
(neon_inv_logic_op2): Likewise.
(arm_anddi_operand_neon): New predicate.
testsuite:
* gcc.target/arm/anddi3-opt.c: New test.
* gcc.target/arm/anddi3-opt2.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@197965 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/arm/predicates.md')
| -rw-r--r-- | gcc/config/arm/predicates.md | 28 |
1 files changed, 17 insertions, 11 deletions
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index f301df2fcdb..2e0de08a8d0 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -31,6 +31,17 @@ || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); }) +(define_predicate "imm_for_neon_inv_logic_operand" + (match_code "const_vector") +{ + return (TARGET_NEON + && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); +}) + +(define_predicate "neon_inv_logic_op2" + (ior (match_operand 0 "imm_for_neon_inv_logic_operand") + (match_operand 0 "s_register_operand"))) + ;; Any hard register. (define_predicate "arm_hard_register_operand" (match_code "reg") @@ -145,6 +156,12 @@ (ior (match_operand 0 "arm_rhs_operand") (match_operand 0 "arm_neg_immediate_operand"))) +(define_predicate "arm_anddi_operand_neon" + (ior (match_operand 0 "s_register_operand") + (and (match_code "const_int") + (match_test "const_ok_for_dimode_op (INTVAL (op), AND)")) + (match_operand 0 "neon_inv_logic_op2"))) + (define_predicate "arm_adddi_operand" (ior (match_operand 0 "s_register_operand") (and (match_code "const_int") @@ -525,21 +542,10 @@ && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); }) -(define_predicate "imm_for_neon_inv_logic_operand" - (match_code "const_vector") -{ - return (TARGET_NEON - && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); -}) - (define_predicate "neon_logic_op2" (ior (match_operand 0 "imm_for_neon_logic_operand") (match_operand 0 "s_register_operand"))) -(define_predicate "neon_inv_logic_op2" - (ior (match_operand 0 "imm_for_neon_inv_logic_operand") - (match_operand 0 "s_register_operand"))) - ;; Predicates for named expanders that overlap multiple ISAs. (define_predicate "cmpdi_operand" |