[Mechanical Patch ARM/AArch64 1/2] Rename load/store scheduling types to encode data size

In the AArch64 backend and scheduling models there is some confusion as to
what the load1/load2 etc. scheduling types refer to. This leads to us using
load1/load2 in two contexts - for a variety of 32-bit, 64-bit and 128-bit
loads in AArch32 and 128-bit loads in AArch64. That leads to an undesirable
confusion in scheduling.

Fixing it is easy, but mechanical and boring. Essentially,

  s/load1/load_4/
  s/load2/load_8/
  s/load3/load_12/
  s/load4/load_16/
  s/store1/store_4/
  s/store2/store_8/
  s/store3/store_12/
  s/store4/store_16/

Across all sorts of pipeline models, and the two backends.

I have intentionally not modified any of the patterns which now look obviously
incorrect. I'll be doing a second pass over the AArch64 back-end in patch
2/2 which will fix these bugs.

---
gcc/

	* config/arm/types.md (type): Rename load1/2/3/4 to load_4/8/12/16
	and store1/2/3/4 to store_4/8/12/16.
	* config/aarch64/aarch64.md: Update for rename.
	* config/arm/arm.md: Likewise.: Likewise.
	* config/arm/arm.c: Likewise.
	* config/arm/thumb1.md: Likewise.
	* config/arm/thumb2.md: Likewise.
	* config/arm/vfp.md: Likewise.
	* config/arm/arm-generic.md: Likewise.
	* config/arm/arm1020e.md: Likewise.
	* config/arm/arm1026ejs.md: Likewise.
	* config/arm/arm1136jfs.md: Likewise.
	* config/arm/arm926ejs.md: Likewise.
	* config/arm/cortex-a15.md: Likewise.
	* config/arm/cortex-a17.md: Likewise.
	* config/arm/cortex-a5.md: Likewise.
	* config/arm/cortex-a53.md: Likewise.
	* config/arm/cortex-a57.md: Likewise.
	* config/arm/cortex-a7.md: Likewise.
	* config/arm/cortex-a8.md: Likewise.
	* config/arm/cortex-a9.md: Likewise.
	* config/arm/cortex-m4.md: Likewise.
	* config/arm/cortex-m7.md: Likewise.
	* config/arm/cortex-r4.md: Likewise.
	* config/arm/exynos-m1.md: Likewise.
	* config/arm/fa526.md: Likewise.
	* config/arm/fa606te.md: Likewise.
	* config/arm/fa626te.md: Likewise.
	* config/arm/fa726te.md: Likewise.
	* config/arm/fmp626.md: Likewise.
	* config/arm/iwmmxt.md: Likewise.
	* config/arm/ldmstm.md: Likewise.
	* config/arm/marvell-pj4.md: Likewise.
	* config/arm/xgene1.md: Likewise.
	* config/aarch64/thunderx.md: Likewise.
	* config/aarch64/thunderx2t99.md: Likewise.
	* config/aarch64/falkor.md: Likewise.

From-SVN: r252025

1 files changed, 8 insertions, 8 deletions

diff --git a/gcc/config/arm/arm926ejs.md b/gcc/config/arm/arm926ejs.md
index 61e93795819..cc5dbee0643 100644
--- a/gcc/config/arm/arm926ejs.md
+++ b/gcc/config/arm/arm926ejs.md
@@ -133,43 +133,43 @@
 ;; most common and (b) the pessimistic assumption will lead to fewer stalls.
 (define_insn_reservation "9_load1_op" 3
  (and (eq_attr "tune" "arm926ejs")
-      (eq_attr "type" "load1,load_byte"))
+      (eq_attr "type" "load_4,load_byte"))
  "e*2,m,w")
 
 (define_insn_reservation "9_store1_op" 0
  (and (eq_attr "tune" "arm926ejs")
-      (eq_attr "type" "store1"))
+      (eq_attr "type" "store_4"))
  "e,m,w")
 
 ;; multiple word loads and stores
 (define_insn_reservation "9_load2_op" 3
  (and (eq_attr "tune" "arm926ejs")
-      (eq_attr "type" "load2"))
+      (eq_attr "type" "load_8"))
  "e,m*2,w")
 
 (define_insn_reservation "9_load3_op" 4
  (and (eq_attr "tune" "arm926ejs")
-      (eq_attr "type" "load3"))
+      (eq_attr "type" "load_12"))
  "e,m*3,w")
 
 (define_insn_reservation "9_load4_op" 5
  (and (eq_attr "tune" "arm926ejs")
-      (eq_attr "type" "load4"))
+      (eq_attr "type" "load_16"))
  "e,m*4,w")
 
 (define_insn_reservation "9_store2_op" 0
  (and (eq_attr "tune" "arm926ejs")
-      (eq_attr "type" "store2"))
+      (eq_attr "type" "store_8"))
  "e,m*2,w")
 
 (define_insn_reservation "9_store3_op" 0
  (and (eq_attr "tune" "arm926ejs")
-      (eq_attr "type" "store3"))
+      (eq_attr "type" "store_12"))
  "e,m*3,w")
 
 (define_insn_reservation "9_store4_op" 0
  (and (eq_attr "tune" "arm926ejs")
-      (eq_attr "type" "store4"))
+      (eq_attr "type" "store_16"))
  "e,m*4,w")
 
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