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| author | Kazu Hirata <kazu@cs.umass.edu> | 2004-02-04 19:46:25 +0000 |
|---|---|---|
| committer | Kazu Hirata <kazu@gcc.gnu.org> | 2004-02-04 19:46:25 +0000 |
| commit | 59b9a953b6338358d0346c91b43095875da7eede (patch) | |
| tree | 225f9eb49e3f815d204a09357409f4f05e10d11a /gcc/config/arm/arm1026ejs.md | |
| parent | e146f815b8fcddac741dfb0b3526a1a46140acdc (diff) | |
| download | gcc-59b9a953b6338358d0346c91b43095875da7eede.tar.gz | |
alpha.c, [...]: Fix comment typos.
* config/alpha/alpha.c, config/arc/arc.c,
config/arm/arm-cores.def, config/arm/arm.c, config/arm/arm.h,
config/arm/arm1026ejs.md, config/arm/arm1136jfs.md,
config/arm/arm926ejs.md, config/arm/vfp.md, config/avr/avr.c,
config/c4x/c4x.c, config/cris/cris.c, config/frv/frv.md,
config/i386/i386.c, config/i386/i386.h, config/i386/i386.md,
config/ia64/ia64.c, config/ia64/unwind-ia64.c,
config/iq2000/iq2000.c, config/m32r/m32r.c,
config/mips/mips.c, config/mmix/mmix.c, config/mmix/mmix.h,
config/ns32k/ns32k.c, config/pa/pa.c, config/pdp11/pdp11.c,
config/rs6000/darwin-ldouble.c, config/rs6000/rs6000.c,
config/rs6000/rs6000.h, config/sparc/sparc.c,
config/vax/vax.c: Fix comment typos. Follow spelling
conventions.
From-SVN: r77267
Diffstat (limited to 'gcc/config/arm/arm1026ejs.md')
| -rw-r--r-- | gcc/config/arm/arm1026ejs.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/arm/arm1026ejs.md b/gcc/config/arm/arm1026ejs.md index 5dd433269ac..77f8fde2ccf 100644 --- a/gcc/config/arm/arm1026ejs.md +++ b/gcc/config/arm/arm1026ejs.md @@ -141,7 +141,7 @@ ;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in ;; the execute stage for five iterations in order to set the flags. -;; The value result is vailable after four iterations. +;; The value result is available after four iterations. (define_insn_reservation "mult6" 4 (and (eq_attr "tune" "arm1026ejs") (eq_attr "insn" "umulls,umlals,smulls,smlals")) @@ -185,7 +185,7 @@ ;; base address is 64-bit aligned; if it is not, an additional cycle ;; is required. This model assumes that the address is always 64-bit ;; aligned. Because the processor can load two registers per cycle, -;; that assumption means that we use the same instruction rservations +;; that assumption means that we use the same instruction reservations ;; for loading 2k and 2k - 1 registers. ;; ;; The ALU pipeline is stalled until the completion of the last memory @@ -233,7 +233,7 @@ "nothing") ;; The latency for a call is not predictable. Therefore, we use 32 as -;; roughly equivalent to postive infinity. +;; roughly equivalent to positive infinity. (define_insn_reservation "call_op" 32 (and (eq_attr "tune" "arm1026ejs") |