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| author | bonzini <bonzini@138bc75d-0d04-0410-961f-82ee72b054a4> | 2009-10-28 10:17:29 +0000 |
|---|---|---|
| committer | bonzini <bonzini@138bc75d-0d04-0410-961f-82ee72b054a4> | 2009-10-28 10:17:29 +0000 |
| commit | 923ffadb74eeb24e64f8b0a7be69a7ee799b0a6c (patch) | |
| tree | 32ba5a71c0fa89fc4ecee255b75f7dee23b2b5cf /gcc/config/arm/arm.md | |
| parent | 0958f2243324358c2658f74a8a870c55c20d3f10 (diff) | |
| download | gcc-923ffadb74eeb24e64f8b0a7be69a7ee799b0a6c.tar.gz | |
2009-10-28 Paolo Bonzini <bonzini@gnu.org>
PR rtl-optimization/40741
* config/arm/arm.c (thumb1_rtx_costs): IOR or XOR with
a small constant is cheap.
* config/arm/arm.md (andsi3, iorsi3): Try to place the result of
force_reg on the LHS.
(xorsi3): Likewise, and split the XOR if the constant is complex
and not in Thumb mode.
2009-10-28 Paolo Bonzini <bonzini@gnu.org>
PR rtl-optimization/40741
* gcc.target/arm/thumb-branch1.c: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@153650 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/arm/arm.md')
| -rw-r--r-- | gcc/config/arm/arm.md | 49 |
1 files changed, 42 insertions, 7 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index e180c2f08f1..fff41d896ca 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1914,7 +1914,16 @@ else /* TARGET_THUMB1 */ { if (GET_CODE (operands[2]) != CONST_INT) - operands[2] = force_reg (SImode, operands[2]); + { + rtx tmp = force_reg (SImode, operands[2]); + if (rtx_equal_p (operands[0], operands[1])) + operands[2] = tmp; + else + { + operands[2] = operands[1]; + operands[1] = tmp; + } + } else { int i; @@ -2623,7 +2632,16 @@ DONE; } else /* TARGET_THUMB1 */ - operands [2] = force_reg (SImode, operands [2]); + { + rtx tmp = force_reg (SImode, operands[2]); + if (rtx_equal_p (operands[0], operands[1])) + operands[2] = tmp; + else + { + operands[2] = operands[1]; + operands[1] = tmp; + } + } } " ) @@ -2731,12 +2749,29 @@ (define_expand "xorsi3" [(set (match_operand:SI 0 "s_register_operand" "") (xor:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "arm_rhs_operand" "")))] + (match_operand:SI 2 "reg_or_int_operand" "")))] "TARGET_EITHER" - "if (TARGET_THUMB1) - if (GET_CODE (operands[2]) == CONST_INT) - operands[2] = force_reg (SImode, operands[2]); - " + "if (GET_CODE (operands[2]) == CONST_INT) + { + if (TARGET_32BIT) + { + arm_split_constant (XOR, SImode, NULL_RTX, + INTVAL (operands[2]), operands[0], operands[1], + optimize && can_create_pseudo_p ()); + DONE; + } + else /* TARGET_THUMB1 */ + { + rtx tmp = force_reg (SImode, operands[2]); + if (rtx_equal_p (operands[0], operands[1])) + operands[2] = tmp; + else + { + operands[2] = operands[1]; + operands[1] = tmp; + } + } + }" ) (define_insn "*arm_xorsi3" |