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| author | rearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-03-13 11:19:23 +0000 |
|---|---|---|
| committer | rearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-03-13 11:19:23 +0000 |
| commit | b4e8a3003fbd33ff6e48543b81d7249797ca035c (patch) | |
| tree | dbf7c69580904f9cdf1218fe8977cffd36e519a0 /gcc/config/arm/arm.h | |
| parent | e9f9125599afd0e7e7e15dd883a8e7cdeda41565 (diff) | |
| download | gcc-b4e8a3003fbd33ff6e48543b81d7249797ca035c.tar.gz | |
* arm.c (arm_legitimate_address_p): New argument, OUTER. Pass through
to arm_legitimate_index_p. Update all callers with SET as default
value.
(arm_legitimate_index_p): New argument, OUTER. Restrict the index
range if OUTER is a sign-extend operation on QImode. Correctly
reject shift operations on sign-extended QImode addresses.
(bad_signed_byte_operand): Delete.
(arm_extendqisi_mem_op): New function.
* arm.h (EXTRA_CONSTRAINT_ARM): Delete. Replace with...
(EXTRA_CONSTRAINT_STR_ARM): ... this. Handle extended address
constraints.
(CONSTRAINT_LEN): New.
(EXTRA_CONSTRAINT): Delete. Replace with...
(EXTRA_CONSTRAINT_STR): ... this.
(PREDICATE_CODES): Remove bad_signed_byte_operand.
* arm.md (extendqihi_insn): Use new constraint Uq. Rework. Length
is now always default.
(define_splits for bad sign-extend loads): Delete.
(arm_extendqisi, arm_extendqisi_v5): Likewise.
* arm/vfp.md (arm_movsi_vfp, arm_movdi_vfp, movsf_vfp, movdf_vfp):
Rework 'U' constraint to 'Uv'.
* arm-protos.h: Remove bad_signed_byte_operand. Add
arm_extendqisi_mem_op.
* doc/md.texi (ARM constraints): Rename VFP constraint (now Uv).
Add Uq constraint.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@79440 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/arm/arm.h')
| -rw-r--r-- | gcc/config/arm/arm.h | 34 |
1 files changed, 20 insertions, 14 deletions
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 4ca25a62dcb..86c6f1403e2 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1471,23 +1471,30 @@ enum reg_class accessed without using a load. 'U' is an address valid for VFP load/store insns. */ -#define EXTRA_CONSTRAINT_ARM(OP, C) \ - ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \ - (C) == 'R' ? (GET_CODE (OP) == MEM \ - && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ - && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \ - (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \ - (C) == 'T' ? cirrus_memory_offset (OP) : \ - (C) == 'U' ? vfp_mem_operand (OP) : \ - 0) +#define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \ + (((C) == 'Q') ? (GET_CODE (OP) == MEM \ + && GET_CODE (XEXP (OP, 0)) == REG) : \ + ((C) == 'R') ? (GET_CODE (OP) == MEM \ + && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ + && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \ + ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \ + ((C) == 'T') ? cirrus_memory_offset (OP) : \ + ((C) == 'U' && (STR)[1] == 'v') ? vfp_mem_operand (OP) : \ + ((C) == 'U' && (STR)[1] == 'q') \ + ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \ + : 0) + +#define CONSTRAINT_LEN(C,STR) \ + ((C) == 'U' ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR)) #define EXTRA_CONSTRAINT_THUMB(X, C) \ ((C) == 'Q' ? (GET_CODE (X) == MEM \ && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0) -#define EXTRA_CONSTRAINT(X, C) \ - (TARGET_ARM ? \ - EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C)) +#define EXTRA_CONSTRAINT_STR(X, C, STR) \ + (TARGET_ARM \ + ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \ + : EXTRA_CONSTRAINT_THUMB (X, C)) #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U') @@ -2336,7 +2343,7 @@ typedef struct #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \ { \ - if (arm_legitimate_address_p (MODE, X, REG_STRICT_P)) \ + if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \ goto WIN; \ } @@ -2817,7 +2824,6 @@ extern int making_const_table; {"thumb_cmpneg_operand", {CONST_INT}}, \ {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \ {"offsettable_memory_operand", {MEM}}, \ - {"bad_signed_byte_operand", {MEM}}, \ {"alignable_memory_operand", {MEM}}, \ {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ |